forked from OSchip/llvm-project
[HardwareLoops] NFC - move loop with irreducible control flow checking logic to HarewareLoopInfo.
llvm-svn: 364415
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6876de90e8
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@ -96,6 +96,7 @@ struct HardwareLoopInfo {
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bool isHardwareLoopCandidate(ScalarEvolution &SE, LoopInfo &LI,
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bool isHardwareLoopCandidate(ScalarEvolution &SE, LoopInfo &LI,
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DominatorTree &DT, bool ForceNestedLoop = false,
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DominatorTree &DT, bool ForceNestedLoop = false,
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bool ForceHardwareLoopPHI = false);
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bool ForceHardwareLoopPHI = false);
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bool canAnalyze(LoopInfo &LI);
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};
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};
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/// This pass provides access to the codegen interfaces that are needed
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/// This pass provides access to the codegen interfaces that are needed
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@ -473,8 +474,7 @@ public:
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/// Query the target whether it would be profitable to convert the given loop
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/// Query the target whether it would be profitable to convert the given loop
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/// into a hardware loop.
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/// into a hardware loop.
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bool isHardwareLoopProfitable(Loop *L, LoopInfo &LI,
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bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE,
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ScalarEvolution &SE,
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AssumptionCache &AC,
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AssumptionCache &AC,
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TargetLibraryInfo *LibInfo,
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TargetLibraryInfo *LibInfo,
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HardwareLoopInfo &HWLoopInfo) const;
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HardwareLoopInfo &HWLoopInfo) const;
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@ -42,6 +42,16 @@ struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
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};
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};
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}
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}
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bool HardwareLoopInfo::canAnalyze(LoopInfo &LI) {
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// If the loop has irreducible control flow, it can not be converted to
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// Hardware loop.
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LoopBlocksRPO RPOT(L);
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RPOT.perform(&LI);
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if (containsIrreducibleCFG<const BasicBlock *>(RPOT, LI))
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return false;
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return true;
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}
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bool HardwareLoopInfo::isHardwareLoopCandidate(ScalarEvolution &SE,
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bool HardwareLoopInfo::isHardwareLoopCandidate(ScalarEvolution &SE,
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LoopInfo &LI, DominatorTree &DT,
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LoopInfo &LI, DominatorTree &DT,
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bool ForceNestedLoop,
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bool ForceNestedLoop,
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@ -218,14 +228,8 @@ bool TargetTransformInfo::isLoweredToCall(const Function *F) const {
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}
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}
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bool TargetTransformInfo::isHardwareLoopProfitable(
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bool TargetTransformInfo::isHardwareLoopProfitable(
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Loop *L, LoopInfo &LI, ScalarEvolution &SE, AssumptionCache &AC,
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Loop *L, ScalarEvolution &SE, AssumptionCache &AC,
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TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const {
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TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const {
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// If the loop has irreducible control flow, it can not be converted to
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// Hardware loop.
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LoopBlocksRPO RPOT(L);
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RPOT.perform(&LI);
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if (containsIrreducibleCFG<const BasicBlock *>(RPOT, LI))
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return false;
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return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
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return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
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}
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}
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@ -198,7 +198,10 @@ bool HardwareLoops::TryConvertLoop(Loop *L) {
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return true; // Stop search.
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return true; // Stop search.
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HardwareLoopInfo HWLoopInfo(L);
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HardwareLoopInfo HWLoopInfo(L);
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if (TTI->isHardwareLoopProfitable(L, *LI, *SE, *AC, LibInfo, HWLoopInfo) ||
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if (!HWLoopInfo.canAnalyze(*LI))
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return false;
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if (TTI->isHardwareLoopProfitable(L, *SE, *AC, LibInfo, HWLoopInfo) ||
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ForceHardwareLoops) {
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ForceHardwareLoops) {
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// Allow overriding of the counter width and loop decrement value.
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// Allow overriding of the counter width and loop decrement value.
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