forked from OSchip/llvm-project
[AMDGPU] Recognize x & (-1 >> (32 - y)) pattern.
Summary: D47980 will canonicalize the `x << (32 - y) >> (32 - y)`, which is the pattern the AMDGPU expects to `x & (-1 >> (32 - y))`, which is not recognized by AMDGPU. Thus, it needs to be recognized, too. Reviewers: nhaehnle, bogner, tstellar, arsenm Reviewed By: arsenm Subscribers: arsenm, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Tags: #amdgpu Differential Revision: https://reviews.llvm.org/D48007 llvm-svn: 334815
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llvm
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@ -682,6 +682,13 @@ multiclass BFEPattern <Instruction UBFE, Instruction SBFE, Instruction MOV> {
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(UBFE $src, $rshift, (MOV (i32 (IMMPopCount $mask))))
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>;
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// x & (-1 >> (bitwidth - y))
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def : AMDGPUPat <
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(and i32:$src, (srl_oneuse -1, (sub 32, i32:$width))),
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(UBFE $src, (i32 0), $width)
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>;
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// x << (bitwidth - y) >> (bitwidth - y)
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def : AMDGPUPat <
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(srl (shl_oneuse i32:$src, (sub 32, i32:$width)), (sub 32, i32:$width)),
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(UBFE $src, (i32 0), $width)
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@ -153,21 +153,11 @@ define i32 @bzhi32_b4_commutative(i32 %val, i32 %numlowbits) nounwind {
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; ---------------------------------------------------------------------------- ;
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define i32 @bzhi32_c0(i32 %val, i32 %numlowbits) nounwind {
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; SI-LABEL: bzhi32_c0:
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; SI: ; %bb.0:
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; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SI-NEXT: v_sub_i32_e32 v1, vcc, 32, v1
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; SI-NEXT: v_lshr_b32_e32 v1, -1, v1
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; SI-NEXT: v_and_b32_e32 v0, v1, v0
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; SI-NEXT: s_setpc_b64 s[30:31]
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;
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; VI-LABEL: bzhi32_c0:
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; VI: ; %bb.0:
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; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; VI-NEXT: v_sub_u32_e32 v1, vcc, 32, v1
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; VI-NEXT: v_lshrrev_b32_e64 v1, v1, -1
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; VI-NEXT: v_and_b32_e32 v0, v1, v0
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; VI-NEXT: s_setpc_b64 s[30:31]
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; GCN-LABEL: bzhi32_c0:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_bfe_u32 v0, v0, 0, v1
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%numhighbits = sub i32 32, %numlowbits
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%mask = lshr i32 -1, %numhighbits
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%masked = and i32 %mask, %val
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@ -200,21 +190,11 @@ define i32 @bzhi32_c1_indexzext(i32 %val, i8 %numlowbits) nounwind {
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}
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define i32 @bzhi32_c4_commutative(i32 %val, i32 %numlowbits) nounwind {
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; SI-LABEL: bzhi32_c4_commutative:
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; SI: ; %bb.0:
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; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SI-NEXT: v_sub_i32_e32 v1, vcc, 32, v1
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; SI-NEXT: v_lshr_b32_e32 v1, -1, v1
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; SI-NEXT: v_and_b32_e32 v0, v0, v1
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; SI-NEXT: s_setpc_b64 s[30:31]
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;
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; VI-LABEL: bzhi32_c4_commutative:
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; VI: ; %bb.0:
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; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; VI-NEXT: v_sub_u32_e32 v1, vcc, 32, v1
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; VI-NEXT: v_lshrrev_b32_e64 v1, v1, -1
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; VI-NEXT: v_and_b32_e32 v0, v0, v1
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; VI-NEXT: s_setpc_b64 s[30:31]
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; GCN-LABEL: bzhi32_c4_commutative:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_bfe_u32 v0, v0, 0, v1
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%numhighbits = sub i32 32, %numlowbits
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%mask = lshr i32 -1, %numhighbits
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%masked = and i32 %val, %mask ; swapped order
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