From aa76cebab59e7ae016a96215b1567b71489a4730 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Thu, 28 Jan 2021 11:10:04 +0000 Subject: [PATCH] Fix "32-bit shift result used in 64-bit comparison" MSVC warning. NFCI. --- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp index 0f5c41527c12..dd4bf517b47c 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -826,7 +826,7 @@ bool RISCVDAGToDAGISel::SelectAddrFI(SDValue Addr, SDValue &Base) { // from PatFrags in tablegen. bool RISCVDAGToDAGISel::isUnneededShiftMask(SDNode *N, unsigned Width) const { assert(N->getOpcode() == ISD::AND && "Unexpected opcode"); - assert(Width >= 5 && N->getValueSizeInBits(0) >= (1 << Width) && + assert(Width >= 5 && N->getValueSizeInBits(0) >= (1ULL << Width) && "Unexpected width"); const APInt &Val = N->getConstantOperandAPInt(1);