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[MC] Add parameter `Address` to MCInstPrinter::printInst 

printInst prints a branch/call instruction as `b offset` (there are many
variants on various targets) instead of `b address`.

It is a convention to use address instead of offset in most external
symbolizers/disassemblers. This difference makes `llvm-objdump -d`
output unsatisfactory.

Add `uint64_t Address` to printInst(), so that it can pass the argument to
printInstruction(). `raw_ostream &OS` is moved to the last to be
consistent with other print* methods.

The next step is to pass `Address` to printInstruction() (generated by
tablegen from the instruction set description). We can gradually migrate
targets to print addresses instead of offsets.

In any case, downstream projects which don't know `Address` can pass 0 as
the argument.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D72172
This commit is contained in:
Fangrui Song 2020-01-03 10:55:30 -08:00
parent dc7b84c66c
commit aa708763d3
54 changed files with 140 additions and 118 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
llvm/include/llvm/MC/MCInstPrinter.h
View File

@ -79,8 +79,8 @@ public:
void setCommentStream(raw_ostream &OS) { CommentStream = &OS; }
/// Print the specified MCInst to the specified raw_ostream.
virtual void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot,
const MCSubtargetInfo &STI) = 0;
virtual void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &OS) = 0;
/// Return the name of the specified opcode enum (e.g. "MOV32ri") or
/// empty if we can't resolve it.

5
llvm/include/llvm/MC/MCStreamer.h
View File

@ -103,8 +103,9 @@ public:
// Allow a target to add behavior to the emitAssignment of MCStreamer.
virtual void emitAssignment(MCSymbol *Symbol, const MCExpr *Value);
virtual void prettyPrintAsm(MCInstPrinter &InstPrinter, raw_ostream &OS,
const MCInst &Inst, const MCSubtargetInfo &STI);
virtual void prettyPrintAsm(MCInstPrinter &InstPrinter, uint64_t Address,
const MCInst &Inst, const MCSubtargetInfo &STI,
raw_ostream &OS);
virtual void emitDwarfFileDirective(StringRef Directive);

4
llvm/lib/MC/MCAsmStreamer.cpp
View File

@ -1944,9 +1944,9 @@ void MCAsmStreamer::EmitInstruction(const MCInst &Inst,
}
if(getTargetStreamer())
getTargetStreamer()->prettyPrintAsm(*InstPrinter, OS, Inst, STI);
getTargetStreamer()->prettyPrintAsm(*InstPrinter, 0, Inst, STI, OS);
else
InstPrinter->printInst(&Inst, OS, "", STI);
InstPrinter->printInst(&Inst, 0, "", STI, OS);
StringRef Comments = CommentToEmit;
if (Comments.size() && Comments.back() != '\n')

3
llvm/lib/MC/MCDisassembler/Disassembler.cpp
View File

@ -277,7 +277,8 @@ size_t LLVMDisasmInstruction(LLVMDisasmContextRef DCR, uint8_t *Bytes,
SmallVector<char, 64> InsnStr;
raw_svector_ostream OS(InsnStr);
formatted_raw_ostream FormattedOS(OS);
IP->printInst(&Inst, FormattedOS, AnnotationsStr, *DC->getSubtargetInfo());
IP->printInst(&Inst, PC, AnnotationsStr, *DC->getSubtargetInfo(),
FormattedOS);
if (DC->getOptions() & LLVMDisassembler_Option_PrintLatency)
emitLatency(DC, Inst);

7
llvm/lib/MC/MCStreamer.cpp
View File

@ -977,9 +977,10 @@ void MCStreamer::EmitAssignment(MCSymbol *Symbol, const MCExpr *Value) {
}
void MCTargetStreamer::prettyPrintAsm(MCInstPrinter &InstPrinter,
raw_ostream &OS, const MCInst &Inst,
const MCSubtargetInfo &STI) {
InstPrinter.printInst(&Inst, OS, "", STI);
uint64_t Address, const MCInst &Inst,
const MCSubtargetInfo &STI,
raw_ostream &OS) {
InstPrinter.printInst(&Inst, Address, "", STI, OS);
}
void MCStreamer::visitUsedSymbol(const MCSymbol &Sym) {

13
llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
View File

@ -56,9 +56,9 @@ void AArch64InstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
OS << getRegisterName(RegNo);
}
void AArch64InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
StringRef Annot,
const MCSubtargetInfo &STI) {
void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annot, const MCSubtargetInfo &STI,
raw_ostream &O) {
// Check for special encodings and print the canonical alias instead.
unsigned Opcode = MI->getOpcode();
@ -704,9 +704,10 @@ static const LdStNInstrDesc *getLdStNInstrDesc(unsigned Opcode) {
return nullptr;
}
void AArch64AppleInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
void AArch64AppleInstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annot,
const MCSubtargetInfo &STI) {
const MCSubtargetInfo &STI,
raw_ostream &O) {
unsigned Opcode = MI->getOpcode();
StringRef Layout;
@ -754,7 +755,7 @@ void AArch64AppleInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
return;
}
AArch64InstPrinter::printInst(MI, O, Annot, STI);
AArch64InstPrinter::printInst(MI, Address, Annot, STI, O);
}
bool AArch64InstPrinter::printSysAlias(const MCInst *MI,

8
llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
View File

@ -25,8 +25,8 @@ public:
AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI);
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
const MCSubtargetInfo &STI) override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override;
void printRegName(raw_ostream &OS, unsigned RegNo) const override;
// Autogenerated by tblgen.
@ -197,8 +197,8 @@ public:
AArch64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI);
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
const MCSubtargetInfo &STI) override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override;
void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
raw_ostream &O) override;

2
llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
View File

@ -344,7 +344,7 @@ void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(), *STI.getInstrInfo(),
*STI.getRegisterInfo());
InstPrinter.printInst(&TmpInst, DisasmStream, StringRef(), STI);
InstPrinter.printInst(&TmpInst, 0, StringRef(), STI, DisasmStream);
// Disassemble instruction/operands to hex representation.
SmallVector<MCFixup, 4> Fixups;

10
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
View File

@ -26,8 +26,9 @@
using namespace llvm;
using namespace llvm::AMDGPU;
void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
StringRef Annot, const MCSubtargetInfo &STI) {
void AMDGPUInstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annot, const MCSubtargetInfo &STI,
raw_ostream &OS) {
OS.flush();
printInstruction(MI, STI, OS);
printAnnotation(OS, Annot);
@ -1342,8 +1343,9 @@ void AMDGPUInstPrinter::printEndpgm(const MCInst *MI, unsigned OpNo,
#include "AMDGPUGenAsmWriter.inc"
void R600InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
StringRef Annot, const MCSubtargetInfo &STI) {
void R600InstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annot, const MCSubtargetInfo &STI,
raw_ostream &O) {
O.flush();
printInstruction(MI, O);
printAnnotation(O, Annot);

8
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
View File

@ -27,8 +27,8 @@ public:
raw_ostream &O);
static const char *getRegisterName(unsigned RegNo);
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
const MCSubtargetInfo &STI) override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override;
static void printRegOperand(unsigned RegNo, raw_ostream &O,
const MCRegisterInfo &MRI);
@ -240,8 +240,8 @@ public:
const MCRegisterInfo &MRI)
: MCInstPrinter(MAI, MII, MRI) {}
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
const MCSubtargetInfo &STI) override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override;
void printInstruction(const MCInst *MI, raw_ostream &O);
static const char *getRegisterName(unsigned RegNo);

5
llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.cpp
View File

@ -97,8 +97,9 @@ void ARCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
OS << StringRef(getRegisterName(RegNo)).lower();
}
void ARCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
StringRef Annot, const MCSubtargetInfo &STI) {
void ARCInstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annot, const MCSubtargetInfo &STI,
raw_ostream &O) {
printInstruction(MI, O);
printAnnotation(O, Annot);
}

4
llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.h
View File

@ -30,8 +30,8 @@ public:
static const char *getRegisterName(unsigned RegNo);
void printRegName(raw_ostream &OS, unsigned RegNo) const override;
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
const MCSubtargetInfo &STI) override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override;
private:
void printMemOperandRI(const MCInst *MI, unsigned OpNum, raw_ostream &O);

5
llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
View File

@ -88,8 +88,9 @@ void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
OS << markup("<reg:") << getRegisterName(RegNo, DefaultAltIdx) << markup(">");
}
void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
StringRef Annot, const MCSubtargetInfo &STI) {
void ARMInstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annot, const MCSubtargetInfo &STI,
raw_ostream &O) {
unsigned Opcode = MI->getOpcode();
switch (Opcode) {

4
llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h
View File

@ -25,8 +25,8 @@ public:
bool applyTargetSpecificCLOption(StringRef Opt) override;
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
const MCSubtargetInfo &STI) override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override;
void printRegName(raw_ostream &OS, unsigned RegNo) const override;
// Autogenerated by tblgen.

5
llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
View File

@ -32,8 +32,9 @@ namespace llvm {
#define PRINT_ALIAS_INSTR
#include "AVRGenAsmWriter.inc"
void AVRInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
StringRef Annot, const MCSubtargetInfo &STI) {
void AVRInstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annot, const MCSubtargetInfo &STI,
raw_ostream &O) {
unsigned Opcode = MI->getOpcode();
// First handle load and store instructions with postinc or predec

4
llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.h
View File

@ -29,8 +29,8 @@ public:
static const char *getPrettyRegisterName(unsigned RegNo,
MCRegisterInfo const &MRI);
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
const MCSubtargetInfo &STI) override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override;
private:
static const char *getRegisterName(unsigned RegNo,

5
llvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.cpp
View File

@ -24,8 +24,9 @@ using namespace llvm;
// Include the auto-generated portion of the assembly writer.
#include "BPFGenAsmWriter.inc"
void BPFInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
StringRef Annot, const MCSubtargetInfo &STI) {
void BPFInstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annot, const MCSubtargetInfo &STI,
raw_ostream &O) {
printInstruction(MI, O);
printAnnotation(O, Annot);
}

4
llvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.h
View File

@ -22,8 +22,8 @@ public:
const MCRegisterInfo &MRI)
: MCInstPrinter(MAI, MII, MRI) {}
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
const MCSubtargetInfo &STI) override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override;
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O,
const char *Modifier = nullptr);
void printMemOperand(const MCInst *MI, int OpNo, raw_ostream &O,

5
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp
View File

@ -30,8 +30,9 @@ void HexagonInstPrinter::printRegName(raw_ostream &O, unsigned RegNo) const {
O << getRegisterName(RegNo);
}
void HexagonInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
StringRef Annot, const MCSubtargetInfo &STI) {
void HexagonInstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annot, const MCSubtargetInfo &STI,
raw_ostream &OS) {
assert(HexagonMCInstrInfo::isBundle(*MI));
assert(HexagonMCInstrInfo::bundleSize(*MI) <= HEXAGON_PACKET_SIZE);
assert(HexagonMCInstrInfo::bundleSize(*MI) > 0);

4
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h
View File

@ -28,8 +28,8 @@ public:
MCRegisterInfo const &MRI)
: MCInstPrinter(MAI, MII, MRI), MII(MII) {}
void printInst(MCInst const *MI, raw_ostream &O, StringRef Annot,
const MCSubtargetInfo &STI) override;
void printInst(MCInst const *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override;
void printRegName(raw_ostream &O, unsigned RegNo) const override;
static char const *getRegisterName(unsigned RegNo);

7
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
View File

@ -137,14 +137,15 @@ public:
MCInstPrinter &IP)
: HexagonTargetStreamer(S) {}
void prettyPrintAsm(MCInstPrinter &InstPrinter, raw_ostream &OS,
const MCInst &Inst, const MCSubtargetInfo &STI) override {
void prettyPrintAsm(MCInstPrinter &InstPrinter, uint64_t Address,
const MCInst &Inst, const MCSubtargetInfo &STI,
raw_ostream &OS) override {
assert(HexagonMCInstrInfo::isBundle(Inst));
assert(HexagonMCInstrInfo::bundleSize(Inst) <= HEXAGON_PACKET_SIZE);
std::string Buffer;
{
raw_string_ostream TempStream(Buffer);
InstPrinter.printInst(&Inst, TempStream, "", STI);
InstPrinter.printInst(&Inst, Address, "", STI, TempStream);
}
StringRef Contents(Buffer);
auto PacketBundle = Contents.rsplit('\n');

5
llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.cpp
View File

@ -137,9 +137,10 @@ bool LanaiInstPrinter::printAlias(const MCInst *MI, raw_ostream &OS) {
}
}
void LanaiInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
void LanaiInstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annotation,
const MCSubtargetInfo & /*STI*/) {
const MCSubtargetInfo & /*STI*/,
raw_ostream &OS) {
if (!printAlias(MI, OS) && !printAliasInstr(MI, OS))
printInstruction(MI, OS);
printAnnotation(OS, Annotation);

4
llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.h
View File

@ -24,8 +24,8 @@ public:
const MCRegisterInfo &MRI)
: MCInstPrinter(MAI, MII, MRI) {}
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
const MCSubtargetInfo &STI) override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override;
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O,
const char *Modifier = nullptr);
void printPredicateOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);

5
llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.cpp
View File

@ -26,8 +26,9 @@ using namespace llvm;
#define PRINT_ALIAS_INSTR
#include "MSP430GenAsmWriter.inc"
void MSP430InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
StringRef Annot, const MCSubtargetInfo &STI) {
void MSP430InstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annot, const MCSubtargetInfo &STI,
raw_ostream &O) {
if (!printAliasInstr(MI, O))
printInstruction(MI, O);
printAnnotation(O, Annot);

4
llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.h
View File

@ -22,8 +22,8 @@ namespace llvm {
const MCRegisterInfo &MRI)
: MCInstPrinter(MAI, MII, MRI) {}
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
const MCSubtargetInfo &STI) override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override;
// Autogenerated by tblgen.
void printInstruction(const MCInst *MI, raw_ostream &O);

5
llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp
View File

@ -75,8 +75,9 @@ void MipsInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
OS << '$' << StringRef(getRegisterName(RegNo)).lower();
}
void MipsInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
StringRef Annot, const MCSubtargetInfo &STI) {
void MipsInstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annot, const MCSubtargetInfo &STI,
raw_ostream &O) {
switch (MI->getOpcode()) {
default:
break;

4
llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h
View File

@ -83,8 +83,8 @@ public:
static const char *getRegisterName(unsigned RegNo);
void printRegName(raw_ostream &OS, unsigned RegNo) const override;
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
const MCSubtargetInfo &STI) override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override;
bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,

5
llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
View File

@ -72,8 +72,9 @@ void NVPTXInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
OS << VReg;
}
void NVPTXInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
StringRef Annot, const MCSubtargetInfo &STI) {
void NVPTXInstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annot, const MCSubtargetInfo &STI,
raw_ostream &OS) {
printInstruction(MI, OS);
// Next always print the annotation.

4
llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
View File

@ -25,8 +25,8 @@ public:
const MCRegisterInfo &MRI);
void printRegName(raw_ostream &OS, unsigned RegNo) const override;
void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot,
const MCSubtargetInfo &STI) override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &OS) override;
// Autogenerated by tblgen.
void printInstruction(const MCInst *MI, raw_ostream &O);

6
llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
View File

@ -64,8 +64,9 @@ void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
OS << RegName;
}
void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
StringRef Annot, const MCSubtargetInfo &STI) {
void PPCInstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annot, const MCSubtargetInfo &STI,
raw_ostream &O) {
// Customize printing of the addis instruction on AIX. When an operand is a
// symbol reference, the instruction syntax is changed to look like a load
// operation, i.e:
@ -197,7 +198,6 @@ void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
printAnnotation(O, Annot);
}
void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O,
const char *Modifier) {

4
llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h
View File

@ -32,8 +32,8 @@ public:
: MCInstPrinter(MAI, MII, MRI), TT(T) {}
void printRegName(raw_ostream &OS, unsigned RegNo) const override;
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
const MCSubtargetInfo &STI) override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override;
// Autogenerated by tblgen.
void printInstruction(const MCInst *MI, raw_ostream &O);

5
llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
View File

@ -63,8 +63,9 @@ bool RISCVInstPrinter::applyTargetSpecificCLOption(StringRef Opt) {
return false;
}
void RISCVInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
StringRef Annot, const MCSubtargetInfo &STI) {
void RISCVInstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annot, const MCSubtargetInfo &STI,
raw_ostream &O) {
bool Res = false;
const MCInst *NewMI = MI;
MCInst UncompressedMI;

4
llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
View File

@ -27,8 +27,8 @@ public:
bool applyTargetSpecificCLOption(StringRef Opt) override;
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
const MCSubtargetInfo &STI) override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override;
void printRegName(raw_ostream &O, unsigned RegNo) const override;
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,

5
llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp
View File

@ -43,8 +43,9 @@ void SparcInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const
OS << '%' << StringRef(getRegisterName(RegNo)).lower();
}
void SparcInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
StringRef Annot, const MCSubtargetInfo &STI) {
void SparcInstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annot, const MCSubtargetInfo &STI,
raw_ostream &O) {
if (!printAliasInstr(MI, STI, O) && !printSparcAliasInstr(MI, STI, O))
printInstruction(MI, STI, O);
printAnnotation(O, Annot);

4
llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h
View File

@ -24,8 +24,8 @@ public:
: MCInstPrinter(MAI, MII, MRI) {}
void printRegName(raw_ostream &OS, unsigned RegNo) const override;
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
const MCSubtargetInfo &STI) override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override;
bool printSparcAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
raw_ostream &OS);
bool isV9(const MCSubtargetInfo &STI) const;

6
llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.cpp
View File

@ -55,9 +55,9 @@ void SystemZInstPrinter::printOperand(const MCOperand &MO, const MCAsmInfo *MAI,
llvm_unreachable("Invalid operand");
}
void SystemZInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
StringRef Annot,
const MCSubtargetInfo &STI) {
void SystemZInstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annot, const MCSubtargetInfo &STI,
raw_ostream &O) {
printInstruction(MI, O);
printAnnotation(O, Annot);
}

4
llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.h
View File

@ -40,8 +40,8 @@ public:
// Override MCInstPrinter.
void printRegName(raw_ostream &O, unsigned RegNo) const override;
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
const MCSubtargetInfo &STI) override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override;
private:
// Print various types of operand.

5
llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp
View File

@ -44,9 +44,10 @@ void WebAssemblyInstPrinter::printRegName(raw_ostream &OS,
OS << "$" << RegNo;
}
void WebAssemblyInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
void WebAssemblyInstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annot,
const MCSubtargetInfo &STI) {
const MCSubtargetInfo &STI,
raw_ostream &OS) {
// Print the instruction (this uses the AsmStrings from the .td files).
printInstruction(MI, OS);

4
llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.h
View File

@ -37,8 +37,8 @@ public:
const MCRegisterInfo &MRI);
void printRegName(raw_ostream &OS, unsigned RegNo) const override;
void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot,
const MCSubtargetInfo &STI) override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &OS) override;
// Used by tblegen code.
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);

5
llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
View File

@ -38,8 +38,9 @@ void X86ATTInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
OS << markup("<reg:") << '%' << getRegisterName(RegNo) << markup(">");
}
void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
StringRef Annot, const MCSubtargetInfo &STI) {
void X86ATTInstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annot, const MCSubtargetInfo &STI,
raw_ostream &OS) {
// If verbose assembly is enabled, we can print some informative comments.
if (CommentStream)
HasCustomInstComment = EmitAnyX86InstComments(MI, *CommentStream, MII);

4
llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.h
View File

@ -24,8 +24,8 @@ public:
: X86InstPrinterCommon(MAI, MII, MRI), HasCustomInstComment(false) {}
void printRegName(raw_ostream &OS, unsigned RegNo) const override;
void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot,
const MCSubtargetInfo &STI) override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &OS) override;
bool printVecCompareInstr(const MCInst *MI, raw_ostream &OS);
// Autogenerated by tblgen, returns true if we successfully printed an

6
llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
View File

@ -36,9 +36,9 @@ void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
OS << getRegisterName(RegNo);
}
void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
StringRef Annot,
const MCSubtargetInfo &STI) {
void X86IntelInstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annot, const MCSubtargetInfo &STI,
raw_ostream &OS) {
printInstFlags(MI, OS);
// In 16-bit mode, print data16 as data32.

4
llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.h
View File

@ -25,8 +25,8 @@ public:
: X86InstPrinterCommon(MAI, MII, MRI) {}
void printRegName(raw_ostream &OS, unsigned RegNo) const override;
void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot,
const MCSubtargetInfo &STI) override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &OS) override;
bool printVecCompareInstr(const MCInst *MI, raw_ostream &OS);
// Autogenerated by tblgen, returns true if we successfully printed an

5
llvm/lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.cpp
View File

@ -30,8 +30,9 @@ void XCoreInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
OS << StringRef(getRegisterName(RegNo)).lower();
}
void XCoreInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
StringRef Annot, const MCSubtargetInfo &STI) {
void XCoreInstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annot, const MCSubtargetInfo &STI,
raw_ostream &O) {
printInstruction(MI, O);
printAnnotation(O, Annot);
}

4
llvm/lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.h
View File

@ -31,8 +31,8 @@ public:
static const char *getRegisterName(unsigned RegNo);
void printRegName(raw_ostream &OS, unsigned RegNo) const override;
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
const MCSubtargetInfo &STI) override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override;
private:
void printInlineJT(const MCInst *MI, int opNum, raw_ostream &O);

2
llvm/tools/llvm-cfi-verify/lib/FileAnalysis.cpp
View File

@ -364,7 +364,7 @@ uint64_t FileAnalysis::indirectCFOperandClobber(const GraphResult &Graph) const
void FileAnalysis::printInstruction(const Instr &InstrMeta,
raw_ostream &OS) const {
Printer->printInst(&InstrMeta.Instruction, OS, "", *SubtargetInfo.get());
Printer->printInst(&InstrMeta.Instruction, 0, "", *SubtargetInfo.get(), OS);
}
Error FileAnalysis::initialiseDisassemblyMembers() {

2
llvm/tools/llvm-exegesis/lib/Analysis.cpp
View File

@ -114,7 +114,7 @@ void Analysis::writeSnippet(raw_ostream &OS, ArrayRef<uint8_t> Bytes,
}
SmallString<128> InstPrinterStr; // FIXME: magic number.
raw_svector_ostream OSS(InstPrinterStr);
InstPrinter_->printInst(&MI, OSS, "", *SubtargetInfo_);
InstPrinter_->printInst(&MI, 0, "", *SubtargetInfo_, OSS);
Bytes = Bytes.drop_front(MISize);
Lines.emplace_back(StringRef(InstPrinterStr).trim());
}

2
llvm/tools/llvm-mca/Views/BottleneckAnalysis.cpp
View File

@ -293,7 +293,7 @@ static void printInstruction(formatted_raw_ostream &FOS,
FOS.PadToColumn(14);
MCIP.printInst(&MCI, InstrStream, "", STI);
MCIP.printInst(&MCI, 0, "", STI, InstrStream);
InstrStream.flush();
if (UseDifferentColor)

2
llvm/tools/llvm-mca/Views/InstructionInfoView.cpp
View File

@ -95,7 +95,7 @@ void InstructionInfoView::printView(raw_ostream &OS) const {
FOS.flush();
}
MCIP.printInst(&Inst, InstrStream, "", STI);
MCIP.printInst(&Inst, 0, "", STI, InstrStream);
InstrStream.flush();
// Consume any tabs or spaces at the beginning of the string.

2
llvm/tools/llvm-mca/Views/ResourcePressureView.cpp
View File

@ -163,7 +163,7 @@ void ResourcePressureView::printResourcePressurePerInst(raw_ostream &OS) const {
printResourcePressure(FOS, Usage / Executions, (J + 1) * 7);
}
MCIP.printInst(&MCI, InstrStream, "", STI);
MCIP.printInst(&MCI, 0, "", STI, InstrStream);
InstrStream.flush();
StringRef Str(Instruction);

4
llvm/tools/llvm-mca/Views/TimelineView.cpp
View File

@ -192,7 +192,7 @@ void TimelineView::printAverageWaitTimes(raw_ostream &OS) const {
for (const MCInst &Inst : Source) {
printWaitTimeEntry(FOS, WaitTime[IID], IID, Executions);
// Append the instruction info at the end of the line.
MCIP.printInst(&Inst, InstrStream, "", STI);
MCIP.printInst(&Inst, 0, "", STI, InstrStream);
InstrStream.flush();
// Consume any tabs or spaces at the beginning of the string.
@ -307,7 +307,7 @@ void TimelineView::printTimeline(raw_ostream &OS) const {
unsigned SourceIndex = IID % Source.size();
printTimelineViewEntry(FOS, Entry, Iteration, SourceIndex);
// Append the instruction info at the end of the line.
MCIP.printInst(&Inst, InstrStream, "", STI);
MCIP.printInst(&Inst, 0, "", STI, InstrStream);
InstrStream.flush();
// Consume any tabs or spaces at the beginning of the string.

2
llvm/tools/llvm-mca/llvm-mca.cpp
View File

@ -474,7 +474,7 @@ int main(int argc, char **argv) {
std::string InstructionStr;
raw_string_ostream SS(InstructionStr);
WithColor::error() << IE.Message << '\n';
IP->printInst(&IE.Inst, SS, "", *STI);
IP->printInst(&IE.Inst, 0, "", *STI, SS);
SS.flush();
WithColor::note()
<< "instruction: " << InstructionStr << '\n';

7
llvm/tools/llvm-objdump/MachODump.cpp
View File

@ -7633,9 +7633,10 @@ static void DisassembleMachO(StringRef Filename, MachOObjectFile *MachOOF,
formatted_raw_ostream FormattedOS(outs());
StringRef AnnotationsStr = Annotations.str();
if (UseThumbTarget)
ThumbIP->printInst(&Inst, FormattedOS, AnnotationsStr, *ThumbSTI);
ThumbIP->printInst(&Inst, PC, AnnotationsStr, *ThumbSTI,
FormattedOS);
else
IP->printInst(&Inst, FormattedOS, AnnotationsStr, *STI);
IP->printInst(&Inst, PC, AnnotationsStr, *STI, FormattedOS);
emitComments(CommentStream, CommentsToEmit, FormattedOS, *AsmInfo);
// Print debug info.
@ -7712,7 +7713,7 @@ static void DisassembleMachO(StringRef Filename, MachOObjectFile *MachOOF,
dumpBytes(makeArrayRef(Bytes.data() + Index, InstSize), outs());
}
StringRef AnnotationsStr = Annotations.str();
IP->printInst(&Inst, outs(), AnnotationsStr, *STI);
IP->printInst(&Inst, PC, AnnotationsStr, *STI, outs());
outs() << "\n";
} else {
unsigned int Arch = MachOOF->getArch();

8
llvm/tools/llvm-objdump/llvm-objdump.cpp
View File

@ -708,7 +708,7 @@ public:
OS.indent(Column < TabStop - 1 ? TabStop - 1 - Column : 7 - Column % 8);
if (MI)
IP.printInst(MI, OS, "", STI);
IP.printInst(MI, Address.Address, "", STI, OS);
else
OS << "\t<unknown>";
}
@ -744,7 +744,7 @@ public:
std::string Buffer;
{
raw_string_ostream TempStream(Buffer);
IP.printInst(MI, TempStream, "", STI);
IP.printInst(MI, Address.Address, "", STI, TempStream);
}
StringRef Contents(Buffer);
// Split off bundle attributes
@ -811,7 +811,7 @@ public:
SmallString<40> InstStr;
raw_svector_ostream IS(InstStr);
IP.printInst(MI, IS, "", STI);
IP.printInst(MI, Address.Address, "", STI, IS);
OS << left_justify(IS.str(), 60);
} else {
@ -865,7 +865,7 @@ public:
dumpBytes(Bytes, OS);
}
if (MI)
IP.printInst(MI, OS, "", STI);
IP.printInst(MI, Address.Address, "", STI, OS);
else
OS << "\t<unknown>";
}