forked from OSchip/llvm-project
[X86] AVX512 fallback for floating-point scalar selects
Summary: In the case where of 'select i1 , f32, f32' or select i1, f64, f64 prefer lowering to masked-moves over branches. Fixes pr30561 Reviewers: igorb, aymanmus, delena Differential Revision: https://reviews.llvm.org/D25310 llvm-svn: 285196
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@ -16149,6 +16149,11 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
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}
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}
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// AVX512 fallback is to lower selects of scalar floats to masked moves.
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if (Cond.getValueType() == MVT::i1 && (VT == MVT::f64 || VT == MVT::f32) &&
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Subtarget.hasAVX512())
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return DAG.getNode(X86ISD::SELECTS, DL, VT, Cond, Op1, Op2);
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if (VT.isVector() && VT.getVectorElementType() == MVT::i1) {
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SDValue Op1Scalar;
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if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
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@ -159,27 +159,23 @@ define i64 @pr30249() {
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ret i64 %v
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}
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define double @pr30561_f64(double %a, double %b, i1 %c) {
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define double @pr30561_f64(double %b, double %a, i1 %c) {
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; CHECK-LABEL: pr30561_f64:
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; CHECK: ## BB#0:
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; CHECK-NEXT: testb $1, %dil
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; CHECK-NEXT: jne LBB11_2
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; CHECK-NEXT: ## BB#1:
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; CHECK-NEXT: vmovaps %xmm1, %xmm0
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; CHECK-NEXT: LBB11_2:
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; CHECK-NEXT: andl $1, %edi
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; CHECK-NEXT: kmovw %edi, %k1
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; CHECK-NEXT: vmovsd %xmm1, %xmm0, %xmm0 {%k1}
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; CHECK-NEXT: retq
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%cond = select i1 %c, double %a, double %b
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ret double %cond
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}
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define float @pr30561_f32(float %a, float %b, i1 %c) {
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define float @pr30561_f32(float %b, float %a, i1 %c) {
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; CHECK-LABEL: pr30561_f32:
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; CHECK: ## BB#0:
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; CHECK-NEXT: testb $1, %dil
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; CHECK-NEXT: jne LBB12_2
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; CHECK-NEXT: ## BB#1:
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; CHECK-NEXT: vmovaps %xmm1, %xmm0
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; CHECK-NEXT: LBB12_2:
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; CHECK-NEXT: andl $1, %edi
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; CHECK-NEXT: kmovw %edi, %k1
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; CHECK-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1}
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; CHECK-NEXT: retq
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%cond = select i1 %c, float %a, float %b
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ret float %cond
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