forked from OSchip/llvm-project
parent
49520b99a3
commit
aa13b6f71b
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@ -163,6 +163,9 @@ void FastISelEmitter::run(std::ostream &OS) {
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CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op->getName());
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if (II.OperandList.empty())
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continue;
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// For now, ignore instructions where the first operand is not an
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// output register.
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Record *Op0Rec = II.OperandList[0].Rec;
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if (!Op0Rec->isSubClassOf("RegisterClass"))
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continue;
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@ -191,7 +194,7 @@ void FastISelEmitter::run(std::ostream &OS) {
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if (!InstPatNode->getPredicateFn().empty())
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continue;
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// Check all the operands. For now only accept register operands.
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// Check all the operands.
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OperandsSignature Operands;
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for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
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TreePatternNode *Op = InstPatNode->getChild(i);
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@ -204,11 +207,15 @@ void FastISelEmitter::run(std::ostream &OS) {
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if (!OpDI)
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goto continue_label;
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Record *OpLeafRec = OpDI->getDef();
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// For now, only accept register operands.
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if (!OpLeafRec->isSubClassOf("RegisterClass"))
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goto continue_label;
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// For now, require the register operands' register classes to all
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// be the same.
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const CodeGenRegisterClass *RC = &Target.getRegisterClass(OpLeafRec);
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if (!RC)
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goto continue_label;
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// For now, all the operands must have the same type.
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if (Op->getTypeNum(0) != VT)
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goto continue_label;
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Operands.Operands.push_back("r");
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