LegalizeDAG: Implement promote for scalar_to_vector

This allows avoiding the default Expand behavior which
introduces stack usage. Bitcast the scalar and replace
the missing elements with undef.

This is covered by existing tests and used by a future
commit which makes 64-bit vectors legal types on AMDGPU.

llvm-svn: 252632
This commit is contained in:
Matt Arsenault 2015-11-10 18:48:11 +00:00
parent a46aa641f2
commit aa118e299c
1 changed files with 28 additions and 0 deletions

View File

@ -4438,6 +4438,34 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
Results.push_back(DAG.getNode(ISD::BITCAST, SL, OVT, NewVec));
break;
}
case ISD::SCALAR_TO_VECTOR: {
MVT EltVT = OVT.getVectorElementType();
MVT NewEltVT = NVT.getVectorElementType();
// Handle bitcasts to different vector type with the smae total bit size.
//
// e.g. v2i64 = scalar_to_vector x:i64
// =>
// concat_vectors (v2i32 bitcast x:i64), (v2i32 undef)
//
MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
SDValue Val = Node->getOperand(0);
SDLoc SL(Node);
SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val);
SDValue Undef = DAG.getUNDEF(MidVT);
SmallVector<SDValue, 8> NewElts;
NewElts.push_back(CastVal);
for (unsigned I = 1, NElts = OVT.getVectorNumElements(); I != NElts; ++I)
NewElts.push_back(Undef);
SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewElts);
SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
Results.push_back(CvtVec);
break;
}
}
// Replace the original node with the legalized result.