forked from OSchip/llvm-project
Fix infinite loop in nested multiclasses.
Patch by Michael Liao! llvm-svn: 152232
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@ -1726,12 +1726,6 @@ void Record::setName(Init *NewName) {
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} // Otherwise this isn't yet registered.
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Name = NewName;
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checkName();
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// Since the Init for the name was changed, see if we can resolve
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// any of it using members of the Record.
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Init *ComputedName = Name->resolveReferences(*this, 0);
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if (ComputedName != Name) {
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setName(ComputedName);
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}
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// DO NOT resolve record values to the name at this point because
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// there might be default values for arguments of this def. Those
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// arguments might not have been resolved yet so we don't want to
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@ -1754,6 +1748,8 @@ void Record::setName(const std::string &Name) {
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/// references.
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void Record::resolveReferencesTo(const RecordVal *RV) {
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for (unsigned i = 0, e = Values.size(); i != e; ++i) {
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if (RV == &Values[i]) // Skip resolve the same field as the given one
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continue;
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if (Init *V = Values[i].getValue())
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Values[i].setValue(V->resolveReferences(*this, RV));
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}
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@ -0,0 +1,46 @@
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// RUN: llvm-tblgen %s | FileCheck %s
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// XFAIL: vg_leak
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class Type<string name, int length, int width> {
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string Name = name;
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int Length = length;
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int Width = width;
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}
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multiclass OT1<string ss, int l, int w> {
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def _#NAME# : Type<ss, l, w>;
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}
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multiclass OT2<string ss, int w> {
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defm v1#NAME# : OT1<!strconcat( "v1", ss), 1, w>;
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defm v2#NAME# : OT1<!strconcat( "v2", ss), 2, w>;
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defm v3#NAME# : OT1<!strconcat( "v3", ss), 3, w>;
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defm v4#NAME# : OT1<!strconcat( "v4", ss), 4, w>;
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defm v8#NAME# : OT1<!strconcat( "v8", ss), 8, w>;
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defm v16#NAME# : OT1<!strconcat("v16", ss), 16, w>;
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}
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defm i8 : OT2<"i8", 8>;
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// CHECK: _v16i8
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// CHECK: Length = 16
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// CHECK: Width = 8
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// CHECK: _v1i8
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// CHECK: Length = 1
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// CHECK: Width = 8
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// CHECK: _v2i8
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// CHECK: Length = 2
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// CHECK: Width = 8
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// CHECK: _v3i8
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// CHECK: Length = 3
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// CHECK: Width = 8
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// CHECK: _v4i8
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// CHECK: Length = 4
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// CHECK: Width = 8
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// CHECK: _v8i8
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// CHECK: Length = 8
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// CHECK: Width = 8
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