forked from OSchip/llvm-project
[GlobalISel] Add support for address-taken basic blocks
To make this work, pointers from the MachineBasicBlock to the LLVM-IR-level basic blocks need to be initialized, as the AsmPrinter uses this link to be able to print out labels for the basic blocks that are address-taken. Most of the changes in this commit are about adapting existing tests to include the basic block name that is now printed out in the MIR format, now that the name becomes available as the link to the LLVM-IR basic block is initialized. The relevant test change for the functionality added in this patch are the added "(address-taken)" strings in test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll. Differential Revision: https://reviews.llvm.org/D28123 llvm-svn: 291105
This commit is contained in:
Kristof Beyls
parent
5e9bfc671b
commit
a983e7c4a4
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@ -125,8 +125,11 @@ unsigned IRTranslator::getMemOpAlignment(const Instruction &I) {
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MachineBasicBlock &IRTranslator::getOrCreateBB(const BasicBlock &BB) {
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MachineBasicBlock *&MBB = BBToMBB[&BB];
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if (!MBB) {
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MBB = MF->CreateMachineBasicBlock();
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MBB = MF->CreateMachineBasicBlock(&BB);
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MF->push_back(MBB);
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if (BB.hasAddressTaken())
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MBB->setHasAddressTaken();
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}
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return *MBB;
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}
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@ -52,10 +52,10 @@ define void @allocai64() {
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; CHECK: body:
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;
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; ABI/constant lowering and IR-level entry basic block.
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; CHECK: {{bb.[0-9]+}}:
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; CHECK: {{bb.[0-9]+}} (%ir-block.{{[0-9]+}}):
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;
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; Make sure we have one successor and only one.
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; CHECK-NEXT: successors: %[[END:bb.[0-9]+]](0x80000000)
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; CHECK-NEXT: successors: %[[END:bb.[0-9]+.end]](0x80000000)
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;
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; Check that we emit the correct branch.
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; CHECK: G_BR %[[END]]
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@ -74,10 +74,10 @@ end:
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; CHECK: body:
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;
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; ABI/constant lowering and IR-level entry basic block.
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; CHECK: {{bb.[0-9]+}}:
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; CHECK: {{bb.[0-9]+}} (%ir-block.{{[0-9]+}}):
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; Make sure we have two successors
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; CHECK-NEXT: successors: %[[TRUE:bb.[0-9]+]](0x40000000),
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; CHECK: %[[FALSE:bb.[0-9]+]](0x40000000)
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; CHECK-NEXT: successors: %[[TRUE:bb.[0-9]+.true]](0x40000000),
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; CHECK: %[[FALSE:bb.[0-9]+.false]](0x40000000)
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;
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; CHECK: [[ADDR:%.*]](p0) = COPY %x0
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;
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@ -105,8 +105,8 @@ false:
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; CHECK-LABEL: name: switch
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; CHECK: body:
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;
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; CHECK: {{bb.[0-9]+}}:
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; CHECK-NEXT: successors: %[[BB_CASE100:bb.[0-9]+]](0x40000000), %[[BB_NOTCASE100_CHECKNEXT:bb.[0-9]+.entry]](0x40000000)
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; CHECK: {{bb.[0-9]+.entry}}:
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; CHECK-NEXT: successors: %[[BB_CASE100:bb.[0-9]+.case100]](0x40000000), %[[BB_NOTCASE100_CHECKNEXT:bb.[0-9]+.entry]](0x40000000)
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; CHECK: %0(s32) = COPY %w0
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; CHECK: %[[reg100:[0-9]+]](s32) = G_CONSTANT i32 100
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; CHECK: %[[reg200:[0-9]+]](s32) = G_CONSTANT i32 200
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@ -118,21 +118,21 @@ false:
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; CHECK: G_BR %[[BB_NOTCASE100_CHECKNEXT]]
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;
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; CHECK: [[BB_CASE100]]:
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; CHECK-NEXT: successors: %[[BB_RET:bb.[0-9]+]](0x80000000)
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; CHECK-NEXT: successors: %[[BB_RET:bb.[0-9]+.return]](0x80000000)
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; CHECK: %[[regretc100:[0-9]+]](s32) = G_ADD %0, %[[reg1]]
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; CHECK: G_BR %[[BB_RET]]
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; CHECK: [[BB_NOTCASE100_CHECKNEXT]]:
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; CHECK-NEXT: successors: %[[BB_CASE200:bb.[0-9]+]](0x40000000), %[[BB_NOTCASE200_CHECKNEXT:bb.[0-9]+.entry]](0x40000000)
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; CHECK-NEXT: successors: %[[BB_CASE200:bb.[0-9]+.case200]](0x40000000), %[[BB_NOTCASE200_CHECKNEXT:bb.[0-9]+.entry]](0x40000000)
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; CHECK: %[[regicmp200:[0-9]+]](s1) = G_ICMP intpred(eq), %[[reg200]](s32), %0
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; CHECK: G_BRCOND %[[regicmp200]](s1), %[[BB_CASE200]]
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; CHECK: G_BR %[[BB_NOTCASE200_CHECKNEXT]]
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;
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; CHECK: [[BB_CASE200]]:
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; CHECK-NEXT: successors: %[[BB_RET:bb.[0-9]+]](0x80000000)
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; CHECK-NEXT: successors: %[[BB_RET:bb.[0-9]+.return]](0x80000000)
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; CHECK: %[[regretc200:[0-9]+]](s32) = G_ADD %0, %[[reg2]]
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; CHECK: G_BR %[[BB_RET]]
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; CHECK: [[BB_NOTCASE200_CHECKNEXT]]:
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; CHECK-NEXT: successors: %[[BB_DEFAULT:bb.[0-9]+]](0x80000000)
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; CHECK-NEXT: successors: %[[BB_DEFAULT:bb.[0-9]+.default]](0x80000000)
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; CHECK: G_BR %[[BB_DEFAULT]]
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;
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; CHECK: [[BB_DEFAULT]]:
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@ -168,7 +168,6 @@ return:
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ret i32 %res
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}
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; Tests for or.
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; CHECK-LABEL: name: ori64
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; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
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@ -292,11 +291,11 @@ define i64* @trivial_bitcast(i8* %a) {
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; CHECK-LABEL: name: trivial_bitcast_with_copy
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; CHECK: [[A:%[0-9]+]](p0) = COPY %x0
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; CHECK: G_BR %[[CAST:bb\.[0-9]+]]
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; CHECK: G_BR %[[CAST:bb\.[0-9]+.cast]]
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; CHECK: [[CAST]]:
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; CHECK: {{%[0-9]+}}(p0) = COPY [[A]]
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; CHECK: G_BR %[[END:bb\.[0-9]+]]
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; CHECK: G_BR %[[END:bb\.[0-9]+.end]]
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; CHECK: [[END]]:
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define i64* @trivial_bitcast_with_copy(i8* %a) {
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@ -393,8 +392,8 @@ define void @intrinsics(i32 %cur, i32 %bits) {
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}
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; CHECK-LABEL: name: test_phi
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; CHECK: G_BRCOND {{%.*}}, %[[TRUE:bb\.[0-9]+]]
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; CHECK: G_BR %[[FALSE:bb\.[0-9]+]]
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; CHECK: G_BRCOND {{%.*}}, %[[TRUE:bb\.[0-9]+.true]]
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; CHECK: G_BR %[[FALSE:bb\.[0-9]+.false]]
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; CHECK: [[TRUE]]:
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; CHECK: [[RES1:%[0-9]+]](s32) = G_LOAD
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@ -1002,7 +1001,7 @@ define void @test_large_const(i128* %addr) {
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; correct.
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define i8* @test_const_placement() {
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; CHECK-LABEL: name: test_const_placement
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; CHECK: bb.{{[0-9]+}}:
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; CHECK: bb.{{[0-9]+}} (%ir-block.{{[0-9]+}}):
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; CHECK: [[VAL_INT:%[0-9]+]](s32) = G_CONSTANT i32 42
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; CHECK: [[VAL:%[0-9]+]](p0) = G_INTTOPTR [[VAL_INT]](s32)
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; CHECK: G_BR
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@ -8,8 +8,8 @@ declare i32 @llvm.eh.typeid.for(i8*)
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; CHECK: name: bar
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; CHECK: body:
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; CHECK-NEXT: bb.1:
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; CHECK: successors: %[[GOOD:bb.[0-9]+]]{{.*}}%[[BAD:bb.[0-9]+]]
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; CHECK-NEXT: bb.1 (%ir-block.0):
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; CHECK: successors: %[[GOOD:bb.[0-9]+.continue]]{{.*}}%[[BAD:bb.[0-9]+.broken]]
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; CHECK: EH_LABEL
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; CHECK: %w0 = COPY
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; CHECK: BL @foo, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0, implicit-def %w0
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@ -24,7 +24,7 @@ define void @test_void_return() {
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; CHECK-NEXT: hasVAStart: false
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; CHECK-NEXT: hasMustTailInVarArgFunc: false
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; CHECK-NEXT: body:
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: bb.1.entry:
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; CHECK-NEXT: RET 0
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entry:
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ret void
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