forked from OSchip/llvm-project
[AArch64] Combine fptoi.sat(fmul) to fixed point cvtf
We already have patterns for fptosi and fptoui plus fmul to fixed point convert, this adds equivalent patterns for fptosi.sat and fptoui.sat, which should apply equally well for the legal saturating variants. Differential Revision: https://reviews.llvm.org/D113199
This commit is contained in:
David Green
parent
4375430689
commit
a982940eb5
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@ -3754,35 +3754,56 @@ defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>;
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// AArch64's FCVT instructions saturate when out of range.
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multiclass FPToIntegerSatPats<SDNode to_int_sat, string INST> {
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let Predicates = [HasFullFP16] in {
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def : Pat<(i32 (to_int_sat f16:$Rn, i32)),
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(!cast<Instruction>(INST # UWHr) f16:$Rn)>;
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def : Pat<(i32 (to_int_sat f32:$Rn, i32)),
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(!cast<Instruction>(INST # UWSr) f32:$Rn)>;
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def : Pat<(i32 (to_int_sat f64:$Rn, i32)),
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(!cast<Instruction>(INST # UWDr) f64:$Rn)>;
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def : Pat<(i64 (to_int_sat f16:$Rn, i64)),
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(!cast<Instruction>(INST # UXHr) f16:$Rn)>;
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}
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def : Pat<(i32 (to_int_sat f32:$Rn, i32)),
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(!cast<Instruction>(INST # UWSr) f32:$Rn)>;
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def : Pat<(i64 (to_int_sat f32:$Rn, i64)),
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(!cast<Instruction>(INST # UXSr) f32:$Rn)>;
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def : Pat<(i32 (to_int_sat f64:$Rn, i32)),
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(!cast<Instruction>(INST # UWDr) f64:$Rn)>;
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def : Pat<(i64 (to_int_sat f64:$Rn, i64)),
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(!cast<Instruction>(INST # UXDr) f64:$Rn)>;
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let Predicates = [HasFullFP16] in {
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def : Pat<(i32 (to_int_sat (fmul f16:$Rn, fixedpoint_f16_i32:$scale), i32)),
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(!cast<Instruction>(INST # SWHri) $Rn, $scale)>;
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def : Pat<(i64 (to_int_sat (fmul f16:$Rn, fixedpoint_f16_i64:$scale), i64)),
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(!cast<Instruction>(INST # SXHri) $Rn, $scale)>;
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}
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def : Pat<(i32 (to_int_sat (fmul f32:$Rn, fixedpoint_f32_i32:$scale), i32)),
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(!cast<Instruction>(INST # SWSri) $Rn, $scale)>;
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def : Pat<(i64 (to_int_sat (fmul f32:$Rn, fixedpoint_f32_i64:$scale), i64)),
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(!cast<Instruction>(INST # SXSri) $Rn, $scale)>;
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def : Pat<(i32 (to_int_sat (fmul f64:$Rn, fixedpoint_f64_i32:$scale), i32)),
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(!cast<Instruction>(INST # SWDri) $Rn, $scale)>;
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def : Pat<(i64 (to_int_sat (fmul f64:$Rn, fixedpoint_f64_i64:$scale), i64)),
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(!cast<Instruction>(INST # SXDri) $Rn, $scale)>;
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}
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defm : FPToIntegerSatPats<fp_to_sint_sat, "FCVTZS">;
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defm : FPToIntegerSatPats<fp_to_uint_sat, "FCVTZU">;
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multiclass FPToIntegerIntPats<Intrinsic round, string INST> {
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let Predicates = [HasFullFP16] in {
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def : Pat<(i32 (round f16:$Rn)), (!cast<Instruction>(INST # UWHr) $Rn)>;
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def : Pat<(i64 (round f16:$Rn)), (!cast<Instruction>(INST # UXHr) $Rn)>;
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}
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def : Pat<(i32 (round f32:$Rn)), (!cast<Instruction>(INST # UWSr) $Rn)>;
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def : Pat<(i64 (round f32:$Rn)), (!cast<Instruction>(INST # UXSr) $Rn)>;
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def : Pat<(i32 (round f64:$Rn)), (!cast<Instruction>(INST # UWDr) $Rn)>;
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def : Pat<(i64 (round f64:$Rn)), (!cast<Instruction>(INST # UXDr) $Rn)>;
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let Predicates = [HasFullFP16] in {
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def : Pat<(i32 (round (fmul f16:$Rn, fixedpoint_f16_i32:$scale))),
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(!cast<Instruction>(INST # SWHri) $Rn, $scale)>;
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def : Pat<(i64 (round (fmul f16:$Rn, fixedpoint_f16_i64:$scale))),
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(!cast<Instruction>(INST # SXHri) $Rn, $scale)>;
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}
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def : Pat<(i32 (round (fmul f32:$Rn, fixedpoint_f32_i32:$scale))),
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(!cast<Instruction>(INST # SWSri) $Rn, $scale)>;
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def : Pat<(i64 (round (fmul f32:$Rn, fixedpoint_f32_i64:$scale))),
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@ -3807,10 +3828,12 @@ multiclass FPToIntegerPats<SDNode to_int, SDNode to_int_sat, SDNode round, strin
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(!cast<Instruction>(INST # UXDr) f64:$Rn)>;
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// These instructions saturate like fp_to_[su]int_sat.
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let Predicates = [HasFullFP16] in {
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def : Pat<(i32 (to_int_sat (round f16:$Rn), i32)),
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(!cast<Instruction>(INST # UWHr) f16:$Rn)>;
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def : Pat<(i64 (to_int_sat (round f16:$Rn), i64)),
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(!cast<Instruction>(INST # UXHr) f16:$Rn)>;
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}
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def : Pat<(i32 (to_int_sat (round f32:$Rn), i32)),
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(!cast<Instruction>(INST # UWSr) f32:$Rn)>;
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def : Pat<(i64 (to_int_sat (round f32:$Rn), i64)),
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@ -679,10 +679,7 @@ declare i64 @llvm.fptosi.sat.i64.f16(half)
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define i32 @fcvtzs_sat_f32_i32_7(float %flt) {
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; CHECK-LABEL: fcvtzs_sat_f32_i32_7:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #1124073472
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; CHECK-NEXT: fmov s1, w8
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; CHECK-NEXT: fmul s0, s0, s1
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; CHECK-NEXT: fcvtzs w0, s0
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; CHECK-NEXT: fcvtzs w0, s0, #7
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; CHECK-NEXT: ret
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%fix = fmul float %flt, 128.0
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%cvt = call i32 @llvm.fptosi.sat.i32.f32(float %fix)
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@ -692,10 +689,7 @@ define i32 @fcvtzs_sat_f32_i32_7(float %flt) {
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define i32 @fcvtzs_sat_f32_i32_32(float %flt) {
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; CHECK-LABEL: fcvtzs_sat_f32_i32_32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #1333788672
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; CHECK-NEXT: fmov s1, w8
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; CHECK-NEXT: fmul s0, s0, s1
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; CHECK-NEXT: fcvtzs w0, s0
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; CHECK-NEXT: fcvtzs w0, s0, #32
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; CHECK-NEXT: ret
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%fix = fmul float %flt, 4294967296.0
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%cvt = call i32 @llvm.fptosi.sat.i32.f32(float %fix)
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@ -705,10 +699,7 @@ define i32 @fcvtzs_sat_f32_i32_32(float %flt) {
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define i64 @fcvtzs_sat_f32_i64_64(float %flt) {
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; CHECK-LABEL: fcvtzs_sat_f32_i64_64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #1602224128
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; CHECK-NEXT: fmov s1, w8
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; CHECK-NEXT: fmul s0, s0, s1
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; CHECK-NEXT: fcvtzs x0, s0
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; CHECK-NEXT: fcvtzs x0, s0, #64
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; CHECK-NEXT: ret
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%fix = fmul float %flt, 18446744073709551616.0
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%cvt = call i64 @llvm.fptosi.sat.i64.f32(float %fix)
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@ -718,10 +709,7 @@ define i64 @fcvtzs_sat_f32_i64_64(float %flt) {
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define i32 @fcvtzs_sat_f64_i32_7(double %dbl) {
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; CHECK-LABEL: fcvtzs_sat_f64_i32_7:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, #4638707616191610880
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; CHECK-NEXT: fmov d1, x8
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; CHECK-NEXT: fmul d0, d0, d1
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; CHECK-NEXT: fcvtzs w0, d0
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; CHECK-NEXT: fcvtzs w0, d0, #7
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; CHECK-NEXT: ret
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%fix = fmul double %dbl, 128.0
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%cvt = call i32 @llvm.fptosi.sat.i32.f64(double %fix)
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@ -731,10 +719,7 @@ define i32 @fcvtzs_sat_f64_i32_7(double %dbl) {
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define i32 @fcvtzs_sat_f64_i32_32(double %dbl) {
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; CHECK-LABEL: fcvtzs_sat_f64_i32_32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, #4751297606875873280
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; CHECK-NEXT: fmov d1, x8
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; CHECK-NEXT: fmul d0, d0, d1
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; CHECK-NEXT: fcvtzs w0, d0
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; CHECK-NEXT: fcvtzs w0, d0, #32
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; CHECK-NEXT: ret
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%fix = fmul double %dbl, 4294967296.0
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%cvt = call i32 @llvm.fptosi.sat.i32.f64(double %fix)
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@ -744,10 +729,7 @@ define i32 @fcvtzs_sat_f64_i32_32(double %dbl) {
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define i64 @fcvtzs_sat_f64_i64_7(double %dbl) {
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; CHECK-LABEL: fcvtzs_sat_f64_i64_7:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, #4638707616191610880
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; CHECK-NEXT: fmov d1, x8
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; CHECK-NEXT: fmul d0, d0, d1
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; CHECK-NEXT: fcvtzs x0, d0
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; CHECK-NEXT: fcvtzs x0, d0, #7
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; CHECK-NEXT: ret
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%fix = fmul double %dbl, 128.0
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%cvt = call i64 @llvm.fptosi.sat.i64.f64(double %fix)
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@ -757,10 +739,7 @@ define i64 @fcvtzs_sat_f64_i64_7(double %dbl) {
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define i64 @fcvtzs_sat_f64_i64_64(double %dbl) {
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; CHECK-LABEL: fcvtzs_sat_f64_i64_64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, #4895412794951729152
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; CHECK-NEXT: fmov d1, x8
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; CHECK-NEXT: fmul d0, d0, d1
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; CHECK-NEXT: fcvtzs x0, d0
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; CHECK-NEXT: fcvtzs x0, d0, #64
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; CHECK-NEXT: ret
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%fix = fmul double %dbl, 18446744073709551616.0
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%cvt = call i64 @llvm.fptosi.sat.i64.f64(double %fix)
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@ -781,10 +760,7 @@ define i32 @fcvtzs_sat_f16_i32_7(half %dbl) {
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;
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; CHECK-FP16-LABEL: fcvtzs_sat_f16_i32_7:
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; CHECK-FP16: // %bb.0:
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; CHECK-FP16-NEXT: adrp x8, .LCPI55_0
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; CHECK-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI55_0]
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; CHECK-FP16-NEXT: fmul h0, h0, h1
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; CHECK-FP16-NEXT: fcvtzs w0, h0
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; CHECK-FP16-NEXT: fcvtzs w0, h0, #7
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; CHECK-FP16-NEXT: ret
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%fix = fmul half %dbl, 128.0
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%cvt = call i32 @llvm.fptosi.sat.i32.f16(half %fix)
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@ -805,10 +781,7 @@ define i32 @fcvtzs_sat_f16_i32_15(half %dbl) {
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;
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; CHECK-FP16-LABEL: fcvtzs_sat_f16_i32_15:
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; CHECK-FP16: // %bb.0:
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; CHECK-FP16-NEXT: adrp x8, .LCPI56_0
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; CHECK-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI56_0]
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; CHECK-FP16-NEXT: fmul h0, h0, h1
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; CHECK-FP16-NEXT: fcvtzs w0, h0
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; CHECK-FP16-NEXT: fcvtzs w0, h0, #15
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; CHECK-FP16-NEXT: ret
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%fix = fmul half %dbl, 32768.0
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%cvt = call i32 @llvm.fptosi.sat.i32.f16(half %fix)
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@ -829,10 +802,7 @@ define i64 @fcvtzs_sat_f16_i64_7(half %dbl) {
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;
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; CHECK-FP16-LABEL: fcvtzs_sat_f16_i64_7:
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; CHECK-FP16: // %bb.0:
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; CHECK-FP16-NEXT: adrp x8, .LCPI57_0
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; CHECK-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI57_0]
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; CHECK-FP16-NEXT: fmul h0, h0, h1
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; CHECK-FP16-NEXT: fcvtzs x0, h0
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; CHECK-FP16-NEXT: fcvtzs x0, h0, #7
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; CHECK-FP16-NEXT: ret
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%fix = fmul half %dbl, 128.0
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%cvt = call i64 @llvm.fptosi.sat.i64.f16(half %fix)
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@ -853,10 +823,7 @@ define i64 @fcvtzs_sat_f16_i64_15(half %dbl) {
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;
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; CHECK-FP16-LABEL: fcvtzs_sat_f16_i64_15:
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; CHECK-FP16: // %bb.0:
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; CHECK-FP16-NEXT: adrp x8, .LCPI58_0
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; CHECK-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI58_0]
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; CHECK-FP16-NEXT: fmul h0, h0, h1
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; CHECK-FP16-NEXT: fcvtzs x0, h0
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; CHECK-FP16-NEXT: fcvtzs x0, h0, #15
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; CHECK-FP16-NEXT: ret
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%fix = fmul half %dbl, 32768.0
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%cvt = call i64 @llvm.fptosi.sat.i64.f16(half %fix)
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@ -875,10 +842,7 @@ declare i64 @llvm.fptoui.sat.i64.f16(half)
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define i32 @fcvtzu_sat_f32_i32_7(float %flt) {
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; CHECK-LABEL: fcvtzu_sat_f32_i32_7:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #1124073472
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; CHECK-NEXT: fmov s1, w8
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; CHECK-NEXT: fmul s0, s0, s1
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; CHECK-NEXT: fcvtzu w0, s0
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; CHECK-NEXT: fcvtzu w0, s0, #7
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; CHECK-NEXT: ret
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%fix = fmul float %flt, 128.0
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%cvt = call i32 @llvm.fptoui.sat.i32.f32(float %fix)
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@ -888,10 +852,7 @@ define i32 @fcvtzu_sat_f32_i32_7(float %flt) {
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define i32 @fcvtzu_sat_f32_i32_32(float %flt) {
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; CHECK-LABEL: fcvtzu_sat_f32_i32_32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #1333788672
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; CHECK-NEXT: fmov s1, w8
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; CHECK-NEXT: fmul s0, s0, s1
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; CHECK-NEXT: fcvtzu w0, s0
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; CHECK-NEXT: fcvtzu w0, s0, #32
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; CHECK-NEXT: ret
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%fix = fmul float %flt, 4294967296.0
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%cvt = call i32 @llvm.fptoui.sat.i32.f32(float %fix)
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@ -901,10 +862,7 @@ define i32 @fcvtzu_sat_f32_i32_32(float %flt) {
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define i64 @fcvtzu_sat_f32_i64_64(float %flt) {
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; CHECK-LABEL: fcvtzu_sat_f32_i64_64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #1602224128
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; CHECK-NEXT: fmov s1, w8
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; CHECK-NEXT: fmul s0, s0, s1
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; CHECK-NEXT: fcvtzu x0, s0
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; CHECK-NEXT: fcvtzu x0, s0, #64
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; CHECK-NEXT: ret
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%fix = fmul float %flt, 18446744073709551616.0
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%cvt = call i64 @llvm.fptoui.sat.i64.f32(float %fix)
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@ -914,10 +872,7 @@ define i64 @fcvtzu_sat_f32_i64_64(float %flt) {
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define i32 @fcvtzu_sat_f64_i32_7(double %dbl) {
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; CHECK-LABEL: fcvtzu_sat_f64_i32_7:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, #4638707616191610880
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; CHECK-NEXT: fmov d1, x8
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; CHECK-NEXT: fmul d0, d0, d1
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; CHECK-NEXT: fcvtzu w0, d0
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; CHECK-NEXT: fcvtzu w0, d0, #7
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; CHECK-NEXT: ret
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%fix = fmul double %dbl, 128.0
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%cvt = call i32 @llvm.fptoui.sat.i32.f64(double %fix)
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@ -927,10 +882,7 @@ define i32 @fcvtzu_sat_f64_i32_7(double %dbl) {
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define i32 @fcvtzu_sat_f64_i32_32(double %dbl) {
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; CHECK-LABEL: fcvtzu_sat_f64_i32_32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, #4751297606875873280
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; CHECK-NEXT: fmov d1, x8
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; CHECK-NEXT: fmul d0, d0, d1
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; CHECK-NEXT: fcvtzu w0, d0
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; CHECK-NEXT: fcvtzu w0, d0, #32
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; CHECK-NEXT: ret
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%fix = fmul double %dbl, 4294967296.0
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%cvt = call i32 @llvm.fptoui.sat.i32.f64(double %fix)
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@ -940,10 +892,7 @@ define i32 @fcvtzu_sat_f64_i32_32(double %dbl) {
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define i64 @fcvtzu_sat_f64_i64_7(double %dbl) {
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; CHECK-LABEL: fcvtzu_sat_f64_i64_7:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, #4638707616191610880
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; CHECK-NEXT: fmov d1, x8
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; CHECK-NEXT: fmul d0, d0, d1
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; CHECK-NEXT: fcvtzu x0, d0
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; CHECK-NEXT: fcvtzu x0, d0, #7
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; CHECK-NEXT: ret
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%fix = fmul double %dbl, 128.0
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%cvt = call i64 @llvm.fptoui.sat.i64.f64(double %fix)
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@ -953,10 +902,7 @@ define i64 @fcvtzu_sat_f64_i64_7(double %dbl) {
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define i64 @fcvtzu_sat_f64_i64_64(double %dbl) {
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; CHECK-LABEL: fcvtzu_sat_f64_i64_64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, #4895412794951729152
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; CHECK-NEXT: fmov d1, x8
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; CHECK-NEXT: fmul d0, d0, d1
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; CHECK-NEXT: fcvtzu x0, d0
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; CHECK-NEXT: fcvtzu x0, d0, #64
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; CHECK-NEXT: ret
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%fix = fmul double %dbl, 18446744073709551616.0
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%cvt = call i64 @llvm.fptoui.sat.i64.f64(double %fix)
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||||
|
|
@ -977,10 +923,7 @@ define i32 @fcvtzu_sat_f16_i32_7(half %dbl) {
|
|||
;
|
||||
; CHECK-FP16-LABEL: fcvtzu_sat_f16_i32_7:
|
||||
; CHECK-FP16: // %bb.0:
|
||||
; CHECK-FP16-NEXT: adrp x8, .LCPI66_0
|
||||
; CHECK-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI66_0]
|
||||
; CHECK-FP16-NEXT: fmul h0, h0, h1
|
||||
; CHECK-FP16-NEXT: fcvtzu w0, h0
|
||||
; CHECK-FP16-NEXT: fcvtzu w0, h0, #7
|
||||
; CHECK-FP16-NEXT: ret
|
||||
%fix = fmul half %dbl, 128.0
|
||||
%cvt = call i32 @llvm.fptoui.sat.i32.f16(half %fix)
|
||||
|
|
@ -1001,10 +944,7 @@ define i32 @fcvtzu_sat_f16_i32_15(half %dbl) {
|
|||
;
|
||||
; CHECK-FP16-LABEL: fcvtzu_sat_f16_i32_15:
|
||||
; CHECK-FP16: // %bb.0:
|
||||
; CHECK-FP16-NEXT: adrp x8, .LCPI67_0
|
||||
; CHECK-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI67_0]
|
||||
; CHECK-FP16-NEXT: fmul h0, h0, h1
|
||||
; CHECK-FP16-NEXT: fcvtzu w0, h0
|
||||
; CHECK-FP16-NEXT: fcvtzu w0, h0, #15
|
||||
; CHECK-FP16-NEXT: ret
|
||||
%fix = fmul half %dbl, 32768.0
|
||||
%cvt = call i32 @llvm.fptoui.sat.i32.f16(half %fix)
|
||||
|
|
@ -1025,10 +965,7 @@ define i64 @fcvtzu_sat_f16_i64_7(half %dbl) {
|
|||
;
|
||||
; CHECK-FP16-LABEL: fcvtzu_sat_f16_i64_7:
|
||||
; CHECK-FP16: // %bb.0:
|
||||
; CHECK-FP16-NEXT: adrp x8, .LCPI68_0
|
||||
; CHECK-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI68_0]
|
||||
; CHECK-FP16-NEXT: fmul h0, h0, h1
|
||||
; CHECK-FP16-NEXT: fcvtzu x0, h0
|
||||
; CHECK-FP16-NEXT: fcvtzu x0, h0, #7
|
||||
; CHECK-FP16-NEXT: ret
|
||||
%fix = fmul half %dbl, 128.0
|
||||
%cvt = call i64 @llvm.fptoui.sat.i64.f16(half %fix)
|
||||
|
|
@ -1049,10 +986,7 @@ define i64 @fcvtzu_sat_f16_i64_15(half %dbl) {
|
|||
;
|
||||
; CHECK-FP16-LABEL: fcvtzu_sat_f16_i64_15:
|
||||
; CHECK-FP16: // %bb.0:
|
||||
; CHECK-FP16-NEXT: adrp x8, .LCPI69_0
|
||||
; CHECK-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI69_0]
|
||||
; CHECK-FP16-NEXT: fmul h0, h0, h1
|
||||
; CHECK-FP16-NEXT: fcvtzu x0, h0
|
||||
; CHECK-FP16-NEXT: fcvtzu x0, h0, #15
|
||||
; CHECK-FP16-NEXT: ret
|
||||
%fix = fmul half %dbl, 32768.0
|
||||
%cvt = call i64 @llvm.fptoui.sat.i64.f16(half %fix)
|
||||
|
|
|
|||
Loading…
Reference in New Issue