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[AArch64][GlobalISel] Make <8 x s8> shifts legal and add selection support.

This commit is contained in:
Amara Emerson 2020-10-01 14:18:38 -07:00
parent 9a2b3bbc59
commit a97e97faed
3 changed files with 50 additions and 2 deletions
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5
llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
View File

@ -1498,6 +1498,8 @@ bool AArch64InstructionSelector::selectVectorSHL(
Opc = ImmVal ? AArch64::SHLv8i16_shift : AArch64::USHLv8i16;
} else if (Ty == LLT::vector(16, 8)) {
Opc = ImmVal ? AArch64::SHLv16i8_shift : AArch64::USHLv16i8;
} else if (Ty == LLT::vector(8, 8)) {
Opc = ImmVal ? AArch64::SHLv8i8_shift : AArch64::USHLv8i8;
} else {
LLVM_DEBUG(dbgs() << "Unhandled G_SHL type");
return false;
@ -1557,6 +1559,9 @@ bool AArch64InstructionSelector::selectVectorAshrLshr(
} else if (Ty == LLT::vector(16, 8)) {
Opc = IsASHR ? AArch64::SSHLv16i8 : AArch64::USHLv16i8;
NegOpc = AArch64::NEGv8i16;
} else if (Ty == LLT::vector(8, 8)) {
Opc = IsASHR ? AArch64::SSHLv8i8 : AArch64::USHLv8i8;
NegOpc = AArch64::NEGv8i8;
} else {
LLVM_DEBUG(dbgs() << "Unhandled G_ASHR type");
return false;

2
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
View File

@ -124,13 +124,13 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
{s32, s32},
{s32, s64},
{s64, s64},
{v8s8, v8s8},
{v16s8, v16s8},
{v4s16, v4s16},
{v8s16, v8s16},
{v2s32, v2s32},
{v4s32, v4s32},
{v2s64, v2s64},
})
.clampScalar(1, s32, s64)
.clampScalar(0, s32, s64)

45
llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
View File

@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
# R UN: llc -O0 -debugify-and-strip-all-safe -march=aarch64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
# RUN: llc -O0 -debugify-and-strip-all-safe -march=aarch64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
---
name: test_shift
body: |
@ -431,3 +431,46 @@ body: |
$q0 = COPY %3(<4 x s32>)
$q1 = COPY %4(<4 x s32>)
...
---
name: test_shl_v8s8
body: |
bb.0:
; CHECK-LABEL: name: test_shl_v8s8
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
; CHECK: [[SHL:%[0-9]+]]:_(<8 x s8>) = G_SHL [[COPY]], [[COPY1]](<8 x s8>)
; CHECK: $d0 = COPY [[SHL]](<8 x s8>)
%0:_(<8 x s8>) = COPY $d0
%1:_(<8 x s8>) = COPY $d1
%2:_(<8 x s8>) = G_SHL %0, %1
$d0 = COPY %2
...
---
name: test_ashr_v8s8
body: |
bb.0:
; CHECK-LABEL: name: test_ashr_v8s8
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
; CHECK: [[ASHR:%[0-9]+]]:_(<8 x s8>) = G_ASHR [[COPY]], [[COPY1]](<8 x s8>)
; CHECK: $d0 = COPY [[ASHR]](<8 x s8>)
%0:_(<8 x s8>) = COPY $d0
%1:_(<8 x s8>) = COPY $d1
%2:_(<8 x s8>) = G_ASHR %0, %1
$d0 = COPY %2
...
---
name: test_lshr_v8s8
body: |
bb.0:
; CHECK-LABEL: name: test_lshr_v8s8
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
; CHECK: [[LSHR:%[0-9]+]]:_(<8 x s8>) = G_LSHR [[COPY]], [[COPY1]](<8 x s8>)
; CHECK: $d0 = COPY [[LSHR]](<8 x s8>)
%0:_(<8 x s8>) = COPY $d0
%1:_(<8 x s8>) = COPY $d1
%2:_(<8 x s8>) = G_LSHR %0, %1
$d0 = COPY %2
...