forked from OSchip/llvm-project
Convert tBX_CALL / tBXr9_CALL to actual pseudoinstructions.
llvm-svn: 132086
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2f6ecea19d
commit
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@ -1222,6 +1222,26 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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}
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return;
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}
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case ARM::tBXr9_CALL:
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case ARM::tBX_CALL: {
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{
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MCInst TmpInst;
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TmpInst.setOpcode(ARM::tMOVr);
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TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
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TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
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OutStreamer.EmitInstruction(TmpInst);
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}
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{
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MCInst TmpInst;
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TmpInst.setOpcode(ARM::tBX);
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TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
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// Add predicate operands.
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TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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TmpInst.addOperand(MCOperand::CreateReg(0));
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OutStreamer.EmitInstruction(TmpInst);
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}
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return;
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}
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case ARM::BMOVPCRXr9_CALL:
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case ARM::BMOVPCRX_CALL: {
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{
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@ -463,11 +463,8 @@ let isCall = 1,
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}
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// ARMv4T
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// FIXME: Should be a pseudo.
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let isCodeGenOnly = 1 in
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def tBX_CALL : TIx2<{?,?,?,?,?}, {?,?}, ?,
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(outs), (ins tGPR:$func, variable_ops), IIC_Br,
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"mov\tlr, pc\n\tbx\t$func",
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def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
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Size4Bytes, IIC_Br,
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[(ARMcall_nolink tGPR:$func)]>,
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Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
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}
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@ -518,11 +515,8 @@ let isCall = 1,
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}
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// ARMv4T
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let isCodeGenOnly = 1 in
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// FIXME: Should be a pseudo.
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def tBXr9_CALL : TIx2<{?,?,?,?,?}, {?,?}, ?,
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(outs), (ins tGPR:$func, variable_ops), IIC_Br,
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"mov\tlr, pc\n\tbx\t$func",
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def tBXr9_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
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Size4Bytes, IIC_Br,
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[(ARMcall_nolink tGPR:$func)]>,
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Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
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}
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