forked from OSchip/llvm-project
[AArch64][GlobalISel] Implement partial support for G_SHUFFLE_VECTOR
This change makes some basic type combinations for G_SHUFFLE_VECTOR legal, and implements them with a very pessimistic TBL2 instruction in the selector. For TBL2, support is also needed to generate constant pool entries and load from them in order to materialize the mask register. Currently supports <2 x s64> and <4 x s32> result types. Differential Revision: https://reviews.llvm.org/D58466 llvm-svn: 354521
This commit is contained in:
Amara Emerson
parent
55cc7eb5cb
commit
a946d057b4
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@ -23,6 +23,7 @@
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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@ -75,6 +76,14 @@ private:
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bool selectMergeValues(MachineInstr &I, MachineRegisterInfo &MRI) const;
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bool selectUnmergeValues(MachineInstr &I, MachineRegisterInfo &MRI) const;
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void collectShuffleMaskIndices(MachineInstr &I, MachineRegisterInfo &MRI,
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SmallVectorImpl<int> &Idxs) const;
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bool selectShuffleVector(MachineInstr &I, MachineRegisterInfo &MRI) const;
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unsigned emitConstantPoolEntry(Constant *CPVal, MachineFunction &MF) const;
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MachineInstr *emitLoadFromConstantPool(Constant *CPVal,
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MachineIRBuilder &MIRBuilder) const;
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ComplexRendererFns selectArithImmed(MachineOperand &Root) const;
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ComplexRendererFns selectAddrModeUnscaled(MachineOperand &Root,
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@ -1696,6 +1705,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I,
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return selectMergeValues(I, MRI);
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case TargetOpcode::G_UNMERGE_VALUES:
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return selectUnmergeValues(I, MRI);
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case TargetOpcode::G_SHUFFLE_VECTOR:
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return selectShuffleVector(I, MRI);
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}
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return false;
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@ -1913,6 +1924,125 @@ bool AArch64InstructionSelector::selectUnmergeValues(
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return true;
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}
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void AArch64InstructionSelector::collectShuffleMaskIndices(
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MachineInstr &I, MachineRegisterInfo &MRI,
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SmallVectorImpl<int> &Idxs) const {
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MachineInstr *MaskDef = MRI.getVRegDef(I.getOperand(3).getReg());
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assert(
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MaskDef->getOpcode() == TargetOpcode::G_BUILD_VECTOR &&
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"G_SHUFFLE_VECTOR should have a constant mask operand as G_BUILD_VECTOR");
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// Find the constant indices.
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for (unsigned i = 1, e = MaskDef->getNumOperands(); i < e; ++i) {
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MachineInstr *ScalarDef = MRI.getVRegDef(MaskDef->getOperand(i).getReg());
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assert(ScalarDef && "Could not find vreg def of shufflevec index op");
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// Look through copies.
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while (ScalarDef->getOpcode() == TargetOpcode::COPY) {
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ScalarDef = MRI.getVRegDef(ScalarDef->getOperand(1).getReg());
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assert(ScalarDef && "Could not find def of copy operand");
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}
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assert(ScalarDef->getOpcode() == TargetOpcode::G_CONSTANT);
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Idxs.push_back(ScalarDef->getOperand(1).getCImm()->getSExtValue());
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}
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}
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unsigned
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AArch64InstructionSelector::emitConstantPoolEntry(Constant *CPVal,
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MachineFunction &MF) const {
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Type *CPTy = CPVal->getType()->getPointerTo();
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unsigned Align = MF.getDataLayout().getPrefTypeAlignment(CPTy);
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if (Align == 0)
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Align = MF.getDataLayout().getTypeAllocSize(CPTy);
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MachineConstantPool *MCP = MF.getConstantPool();
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return MCP->getConstantPoolIndex(CPVal, Align);
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}
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MachineInstr *AArch64InstructionSelector::emitLoadFromConstantPool(
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Constant *CPVal, MachineIRBuilder &MIRBuilder) const {
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unsigned CPIdx = emitConstantPoolEntry(CPVal, MIRBuilder.getMF());
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auto Adrp =
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MIRBuilder.buildInstr(AArch64::ADRP, {&AArch64::GPR64RegClass}, {})
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.addConstantPoolIndex(CPIdx, 0, AArch64II::MO_PAGE);
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auto Load =
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MIRBuilder.buildInstr(AArch64::LDRQui, {&AArch64::FPR128RegClass}, {Adrp})
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.addConstantPoolIndex(CPIdx, 0,
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AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
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constrainSelectedInstRegOperands(*Adrp, TII, TRI, RBI);
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constrainSelectedInstRegOperands(*Load, TII, TRI, RBI);
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return &*Load;
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}
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bool AArch64InstructionSelector::selectShuffleVector(
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MachineInstr &I, MachineRegisterInfo &MRI) const {
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const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
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unsigned Src1Reg = I.getOperand(1).getReg();
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const LLT Src1Ty = MRI.getType(Src1Reg);
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unsigned Src2Reg = I.getOperand(2).getReg();
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const LLT Src2Ty = MRI.getType(Src2Reg);
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MachineBasicBlock &MBB = *I.getParent();
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MachineFunction &MF = *MBB.getParent();
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LLVMContext &Ctx = MF.getFunction().getContext();
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// G_SHUFFLE_VECTOR doesn't really have a strictly enforced constant mask
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// operand, it comes in as a normal vector value which we have to analyze to
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// find the mask indices.
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SmallVector<int, 8> Mask;
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collectShuffleMaskIndices(I, MRI, Mask);
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assert(!Mask.empty() && "Expected to find mask indices");
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// G_SHUFFLE_VECTOR is weird in that the source operands can be scalars, if
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// it's originated from a <1 x T> type. Those should have been lowered into
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// G_BUILD_VECTOR earlier.
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if (!Src1Ty.isVector() || !Src2Ty.isVector()) {
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LLVM_DEBUG(dbgs() << "Could not select a \"scalar\" G_SHUFFLE_VECTOR\n");
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return false;
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}
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unsigned BytesPerElt = DstTy.getElementType().getSizeInBits() / 8;
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SmallVector<Constant *, 64> CstIdxs;
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for (int Val : Mask) {
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for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {
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unsigned Offset = Byte + Val * BytesPerElt;
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CstIdxs.emplace_back(ConstantInt::get(Type::getInt8Ty(Ctx), Offset));
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}
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}
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if (DstTy.getSizeInBits() != 128) {
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assert(DstTy.getSizeInBits() == 64 && "Unexpected shuffle result ty");
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// This case can be done with TBL1.
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return false;
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}
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// Use a constant pool to load the index vector for TBL.
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Constant *CPVal = ConstantVector::get(CstIdxs);
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MachineIRBuilder MIRBuilder(I);
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MachineInstr *IndexLoad = emitLoadFromConstantPool(CPVal, MIRBuilder);
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if (!IndexLoad) {
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LLVM_DEBUG(dbgs() << "Could not load from a constant pool");
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return false;
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}
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// For TBL2 we need to emit a REG_SEQUENCE to tie together two consecutive
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// Q registers for regalloc.
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auto RegSeq = MIRBuilder
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.buildInstr(TargetOpcode::REG_SEQUENCE,
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{&AArch64::QQRegClass}, {Src1Reg})
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.addImm(AArch64::qsub0)
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.addUse(Src2Reg)
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.addImm(AArch64::qsub1);
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auto TBL2 =
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MIRBuilder.buildInstr(AArch64::TBLv16i8Two, {I.getOperand(0).getReg()},
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{RegSeq, IndexLoad->getOperand(0).getReg()});
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constrainSelectedInstRegOperands(*RegSeq, TII, TRI, RBI);
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constrainSelectedInstRegOperands(*TBL2, TII, TRI, RBI);
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I.eraseFromParent();
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return true;
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}
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bool AArch64InstructionSelector::selectBuildVector(
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MachineInstr &I, MachineRegisterInfo &MRI) const {
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assert(I.getOpcode() == TargetOpcode::G_BUILD_VECTOR);
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@ -461,6 +461,29 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
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{s32, s64, v8s8, v16s8, v4s16, v8s16, v2s32, v4s32})
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.scalarize(1);
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getActionDefinitionsBuilder(G_SHUFFLE_VECTOR)
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.legalIf([=](const LegalityQuery &Query) {
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const LLT &DstTy = Query.Types[0];
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const LLT &SrcTy = Query.Types[1];
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// For now just support the TBL2 variant which needs the source vectors
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// to be the same size as the dest.
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if (DstTy != SrcTy)
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return false;
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ArrayRef<LLT> SupportedDstTys = {v2s32, v4s32, v2s64};
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for (auto &Ty : SupportedDstTys) {
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if (DstTy == Ty)
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return true;
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}
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return false;
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})
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// G_SHUFFLE_VECTOR can have scalar sources (from 1 x s vectors), we
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// just want those lowered into G_BUILD_VECTOR
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.lowerIf([=](const LegalityQuery &Query) {
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return !Query.Types[1].isVector();
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})
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.clampNumElements(0, v4s32, v4s32)
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.clampNumElements(0, v2s64, v2s64);
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computeTables();
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verify(*ST.getInstrInfo());
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}
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@ -0,0 +1,54 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=aarch64 -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s
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---
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name: shuffle_v4i32
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $q0, $q1
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; CHECK-LABEL: name: shuffle_v4i32
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; CHECK: liveins: $q0, $q1
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
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; CHECK: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<4 x s32>), [[COPY1]], [[BUILD_VECTOR]](<4 x s32>)
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; CHECK: $q0 = COPY [[SHUF]](<4 x s32>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<4 x s32>) = COPY $q0
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%1:_(<4 x s32>) = COPY $q1
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%4:_(s32) = G_CONSTANT i32 0
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%3:_(<4 x s32>) = G_BUILD_VECTOR %4(s32), %4(s32), %4(s32), %4(s32)
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%2:_(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, %3(<4 x s32>)
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$q0 = COPY %2(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: shuffle_v2i64
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $q0, $q1
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; CHECK-LABEL: name: shuffle_v2i64
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; CHECK: liveins: $q0, $q1
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
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; CHECK: [[SHUF:%[0-9]+]]:_(<2 x s64>) = G_SHUFFLE_VECTOR [[COPY]](<2 x s64>), [[COPY1]], [[BUILD_VECTOR]](<2 x s32>)
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; CHECK: $q0 = COPY [[SHUF]](<2 x s64>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<2 x s64>) = COPY $q0
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%1:_(<2 x s64>) = COPY $q1
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%4:_(s32) = G_CONSTANT i32 0
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%3:_(<2 x s32>) = G_BUILD_VECTOR %4(s32), %4(s32)
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%2:_(<2 x s64>) = G_SHUFFLE_VECTOR %0(<2 x s64>), %1, %3(<2 x s32>)
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$q0 = COPY %2(<2 x s64>)
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RET_ReallyLR implicit $q0
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...
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@ -313,7 +313,7 @@
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# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
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#
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# DEBUG-NEXT: G_SHUFFLE_VECTOR (opcode {{[0-9]+}}): 3 type indices
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# DEBUG: .. type index coverage check SKIPPED: no rules defined
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# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
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#
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# DEBUG-NEXT: G_CTTZ (opcode {{[0-9]+}}): 2 type indices
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# DEBUG: .. type index coverage check SKIPPED: no rules defined
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@ -0,0 +1,151 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -global-isel-abort=1 -o - | FileCheck %s
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--- |
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; ModuleID = 'shufflevec-only-legal.ll'
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source_filename = "shufflevec-only-legal.ll"
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64"
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define <4 x i32> @shuffle_v4i32(<4 x i32> %a, <4 x i32> %b) {
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%shuf = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 3, i32 0>
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ret <4 x i32> %shuf
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}
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define <4 x i32> @shuffle_tbl_v4i32(<4 x i32> %a, <4 x i32> %b) {
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%shuf = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 5, i32 7, i32 1, i32 0>
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ret <4 x i32> %shuf
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}
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define <2 x i64> @shuffle_v2i64(<2 x i64> %a, <2 x i64> %b) {
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%shuf = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> zeroinitializer
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ret <2 x i64> %shuf
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}
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...
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---
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name: shuffle_v4i32
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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- { id: 2, class: fpr }
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- { id: 3, class: fpr }
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- { id: 4, class: gpr }
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- { id: 5, class: gpr }
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- { id: 6, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $q0, $q1
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; CHECK-LABEL: name: shuffle_v4i32
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; CHECK: constants:
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; CHECK: value: '<16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 12, i8 13, i8 14, i8 15, i8 0, i8 1, i8 2, i8 3>'
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; CHECK: alignment: 8
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; CHECK: isTargetSpecific: false
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; CHECK: liveins: $q0, $q1
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
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; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
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; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
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; CHECK: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE [[COPY]], %subreg.qsub0, [[COPY1]], %subreg.qsub1
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; CHECK: [[TBLv16i8Two:%[0-9]+]]:fpr128 = TBLv16i8Two [[REG_SEQUENCE]], [[LDRQui]]
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; CHECK: $q0 = COPY [[TBLv16i8Two]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<4 x s32>) = COPY $q0
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%1:fpr(<4 x s32>) = COPY $q1
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%4:gpr(s32) = G_CONSTANT i32 0
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%5:gpr(s32) = G_CONSTANT i32 1
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%6:gpr(s32) = G_CONSTANT i32 3
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%3:fpr(<4 x s32>) = G_BUILD_VECTOR %4(s32), %5(s32), %6(s32), %4(s32)
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%2:fpr(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, %3(<4 x s32>)
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$q0 = COPY %2(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: shuffle_tbl_v4i32
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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- { id: 2, class: fpr }
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- { id: 3, class: fpr }
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- { id: 4, class: gpr }
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- { id: 5, class: gpr }
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- { id: 6, class: gpr }
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- { id: 7, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $q0, $q1
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; CHECK-LABEL: name: shuffle_tbl_v4i32
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; CHECK: constants:
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; CHECK: value: '<16 x i8> <i8 20, i8 21, i8 22, i8 23, i8 28, i8 29, i8 30, i8 31, i8 4, i8 5, i8 6, i8 7, i8 0, i8 1, i8 2, i8 3>'
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; CHECK: alignment: 8
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; CHECK: isTargetSpecific: false
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; CHECK: liveins: $q0, $q1
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
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; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
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; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
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; CHECK: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE [[COPY]], %subreg.qsub0, [[COPY1]], %subreg.qsub1
|
||||
; CHECK: [[TBLv16i8Two:%[0-9]+]]:fpr128 = TBLv16i8Two [[REG_SEQUENCE]], [[LDRQui]]
|
||||
; CHECK: $q0 = COPY [[TBLv16i8Two]]
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%0:fpr(<4 x s32>) = COPY $q0
|
||||
%1:fpr(<4 x s32>) = COPY $q1
|
||||
%4:gpr(s32) = G_CONSTANT i32 5
|
||||
%5:gpr(s32) = G_CONSTANT i32 7
|
||||
%6:gpr(s32) = G_CONSTANT i32 1
|
||||
%7:gpr(s32) = G_CONSTANT i32 0
|
||||
%3:fpr(<4 x s32>) = G_BUILD_VECTOR %4(s32), %5(s32), %6(s32), %7(s32)
|
||||
%2:fpr(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, %3(<4 x s32>)
|
||||
$q0 = COPY %2(<4 x s32>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: shuffle_v2i64
|
||||
alignment: 2
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: fpr }
|
||||
- { id: 1, class: fpr }
|
||||
- { id: 2, class: fpr }
|
||||
- { id: 3, class: fpr }
|
||||
- { id: 4, class: gpr }
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: $q0, $q1
|
||||
|
||||
; CHECK-LABEL: name: shuffle_v2i64
|
||||
; CHECK: constants:
|
||||
; CHECK: value: '<16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7>'
|
||||
; CHECK: alignment: 8
|
||||
; CHECK: isTargetSpecific: false
|
||||
; CHECK: liveins: $q0, $q1
|
||||
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
|
||||
; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
|
||||
; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE [[COPY]], %subreg.qsub0, [[COPY1]], %subreg.qsub1
|
||||
; CHECK: [[TBLv16i8Two:%[0-9]+]]:fpr128 = TBLv16i8Two [[REG_SEQUENCE]], [[LDRQui]]
|
||||
; CHECK: $q0 = COPY [[TBLv16i8Two]]
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%0:fpr(<2 x s64>) = COPY $q0
|
||||
%1:fpr(<2 x s64>) = COPY $q1
|
||||
%4:gpr(s32) = G_CONSTANT i32 0
|
||||
%3:fpr(<2 x s32>) = G_BUILD_VECTOR %4(s32), %4(s32)
|
||||
%2:fpr(<2 x s64>) = G_SHUFFLE_VECTOR %0(<2 x s64>), %1, %3(<2 x s32>)
|
||||
$q0 = COPY %2(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue