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[AMDGPU][MC][GFX9] Added buffer_*_format_d16_hi_x 

See bug 36835: https://bugs.llvm.org/show_bug.cgi?id=36835

Differential Revision: https://reviews.llvm.org/D44825

Reviewers: artem.tamazov, arsenm, timcorringham
llvm-svn: 328707
This commit is contained in:
Dmitry Preobrazhensky 2018-03-28 14:53:13 +00:00
parent ec978e2226
commit a917e88585
3 changed files with 80 additions and 0 deletions
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10
llvm/lib/Target/AMDGPU/BUFInstructions.td
View File

@ -949,6 +949,13 @@ defm BUFFER_STORE_SHORT_D16_HI : MUBUF_Pseudo_Stores <
"buffer_store_short_d16_hi", VGPR_32, i32
>;
defm BUFFER_LOAD_FORMAT_D16_HI_X : MUBUF_Pseudo_Loads <
"buffer_load_format_d16_hi_x", VGPR_32
>;
defm BUFFER_STORE_FORMAT_D16_HI_X : MUBUF_Pseudo_Stores <
"buffer_store_format_d16_hi_x", VGPR_32
>;
} // End HasD16LoadStore
def BUFFER_WBINVL1 : MUBUF_Invalidate <"buffer_wbinvl1",
@ -1946,6 +1953,9 @@ defm BUFFER_LOAD_SBYTE_D16_HI : MUBUF_Real_AllAddr_vi <0x23>;
defm BUFFER_LOAD_SHORT_D16 : MUBUF_Real_AllAddr_vi <0x24>;
defm BUFFER_LOAD_SHORT_D16_HI : MUBUF_Real_AllAddr_vi <0x25>;
defm BUFFER_LOAD_FORMAT_D16_HI_X : MUBUF_Real_AllAddr_vi <0x26>;
defm BUFFER_STORE_FORMAT_D16_HI_X : MUBUF_Real_AllAddr_vi <0x27>;
defm BUFFER_ATOMIC_SWAP : MUBUF_Real_Atomic_vi <0x40>;
defm BUFFER_ATOMIC_CMPSWAP : MUBUF_Real_Atomic_vi <0x41>;
defm BUFFER_ATOMIC_ADD : MUBUF_Real_Atomic_vi <0x42>;

48
llvm/test/MC/AMDGPU/mubuf-gfx9.s
View File

@ -32,3 +32,51 @@ buffer_store_byte_d16_hi v1, off, s[4:7], s1
buffer_store_short_d16_hi v1, off, s[4:7], s1
// GFX9: buffer_store_short_d16_hi v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x6c,0xe0,0x00,0x01,0x01,0x01]
// VI-ERR: error: instruction not supported on this GPU
buffer_load_format_d16_hi_x v5, off, s[8:11], s3
// GFX9: buffer_load_format_d16_hi_x v5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x98,0xe0,0x00,0x05,0x02,0x03]
// VI-ERR: error: instruction not supported on this GPU
buffer_load_format_d16_hi_x v5, off, s[8:11], s3 offset:4095
// GFX9: buffer_load_format_d16_hi_x v5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x98,0xe0,0x00,0x05,0x02,0x03]
// VI-ERR: error
buffer_load_format_d16_hi_x v5, v0, s[8:11], s3 idxen offset:4095
// GFX9: buffer_load_format_d16_hi_x v5, v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x98,0xe0,0x00,0x05,0x02,0x03]
// VI-ERR: error
buffer_load_format_d16_hi_x v5, v0, s[8:11], s3 offen offset:4095
// GFX9: buffer_load_format_d16_hi_x v5, v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x98,0xe0,0x00,0x05,0x02,0x03]
// VI-ERR: error
buffer_load_format_d16_hi_x v5, off, s[8:11], s3 offset:4095 glc
// GFX9: buffer_load_format_d16_hi_x v5, off, s[8:11], s3 offset:4095 glc ; encoding: [0xff,0x4f,0x98,0xe0,0x00,0x05,0x02,0x03]
// VI-ERR: error
buffer_load_format_d16_hi_x v5, off, s[8:11], s3 offset:4095 slc
// GFX9: buffer_load_format_d16_hi_x v5, off, s[8:11], s3 offset:4095 slc ; encoding: [0xff,0x0f,0x9a,0xe0,0x00,0x05,0x02,0x03]
// VI-ERR: error
buffer_store_format_d16_hi_x v255, off, s[12:15], s4
// GFX9: buffer_store_format_d16_hi_x v255, off, s[12:15], s4 ; encoding: [0x00,0x00,0x9c,0xe0,0x00,0xff,0x03,0x04]
// VI-ERR: error: instruction not supported on this GPU
buffer_store_format_d16_hi_x v255, off, s[12:15], s4 offset:4095
// GFX9: buffer_store_format_d16_hi_x v255, off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x9c,0xe0,0x00,0xff,0x03,0x04]
// VI-ERR: error
buffer_store_format_d16_hi_x v1, v0, s[12:15], s4 idxen offset:4095
// GFX9: buffer_store_format_d16_hi_x v1, v0, s[12:15], s4 idxen offset:4095 ; encoding: [0xff,0x2f,0x9c,0xe0,0x00,0x01,0x03,0x04]
// VI-ERR: error
buffer_store_format_d16_hi_x v1, v0, s[12:15], s4 offen offset:4095
// GFX9: buffer_store_format_d16_hi_x v1, v0, s[12:15], s4 offen offset:4095 ; encoding: [0xff,0x1f,0x9c,0xe0,0x00,0x01,0x03,0x04]
// VI-ERR: error
buffer_store_format_d16_hi_x v1, off, s[12:15], s4 offset:4095 glc
// GFX9: buffer_store_format_d16_hi_x v1, off, s[12:15], s4 offset:4095 glc ; encoding: [0xff,0x4f,0x9c,0xe0,0x00,0x01,0x03,0x04]
// VI-ERR: error
buffer_store_format_d16_hi_x v1, off, s[12:15], s4 offset:4095 slc
// GFX9: buffer_store_format_d16_hi_x v1, off, s[12:15], s4 offset:4095 slc ; encoding: [0xff,0x0f,0x9e,0xe0,0x00,0x01,0x03,0x04]
// VI-ERR: error

22
llvm/test/MC/Disassembler/AMDGPU/mubuf_gfx9.txt Normal file
View File

@ -0,0 +1,22 @@
# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX9
# GFX9: buffer_load_format_d16_hi_x v5, off, s[8:11], s3 offset:4095 glc slc ; encoding: [0xff,0x4f,0x9a,0xe0,0x00,0x05,0x02,0x03]
0xff,0x4f,0x9a,0xe0,0x00,0x05,0x02,0x03
# GFX9: buffer_load_format_d16_hi_x v5, v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x98,0xe0,0x00,0x05,0x02,0x03]
0xff,0x2f,0x98,0xe0,0x00,0x05,0x02,0x03
# GFX9: buffer_load_format_d16_hi_x v5, v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x98,0xe0,0x00,0x05,0x02,0x03]
0xff,0x1f,0x98,0xe0,0x00,0x05,0x02,0x03
# GFX9: buffer_store_format_d16_hi_x v1, v0, s[12:15], s4 idxen offset:4095 ; encoding: [0xff,0x2f,0x9c,0xe0,0x00,0x01,0x03,0x04]
0xff,0x2f,0x9c,0xe0,0x00,0x01,0x03,0x04
# GFX9: buffer_store_format_d16_hi_x v1, v0, s[12:15], s4 offen offset:4095 ; encoding: [0xff,0x1f,0x9c,0xe0,0x00,0x01,0x03,0x04]
0xff,0x1f,0x9c,0xe0,0x00,0x01,0x03,0x04
# GFX9: buffer_store_format_d16_hi_x v1, off, s[12:15], s4 offset:4095 glc ; encoding: [0xff,0x4f,0x9c,0xe0,0x00,0x01,0x03,0x04]
0xff,0x4f,0x9c,0xe0,0x00,0x01,0x03,0x04
# GFX9: buffer_store_format_d16_hi_x v1, off, s[12:15], s4 offset:4095 slc ; encoding: [0xff,0x0f,0x9e,0xe0,0x00,0x01,0x03,0x04]
0xff,0x0f,0x9e,0xe0,0x00,0x01,0x03,0x04