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NEON VLD3 lane-indexed assembly parsing and encoding. 

llvm-svn: 148734
This commit is contained in:
Jim Grosbach 2012-01-23 21:53:26 +00:00
parent 3c47e37387
commit a8b444b08b
3 changed files with 299 additions and 10 deletions
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103
llvm/lib/Target/ARM/ARMInstrNEON.td
View File

@ -184,6 +184,7 @@ def VecListOneDWordIndexed : Operand<i32> {
let ParserMatchClass = VecListOneDWordIndexAsmOperand; let ParserMatchClass = VecListOneDWordIndexAsmOperand;
let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
} }
// Register list of two D registers with byte lane subscripting. // Register list of two D registers with byte lane subscripting.
def VecListTwoDByteIndexAsmOperand : AsmOperandClass { def VecListTwoDByteIndexAsmOperand : AsmOperandClass {
let Name = "VecListTwoDByteIndexed"; let Name = "VecListTwoDByteIndexed";
@ -235,6 +236,59 @@ def VecListTwoQWordIndexed : Operand<i32> {
let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
} }
// Register list of three D registers with byte lane subscripting.
def VecListThreeDByteIndexAsmOperand : AsmOperandClass {
let Name = "VecListThreeDByteIndexed";
let ParserMethod = "parseVectorList";
let RenderMethod = "addVecListIndexedOperands";
}
def VecListThreeDByteIndexed : Operand<i32> {
let ParserMatchClass = VecListThreeDByteIndexAsmOperand;
let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
}
// ...with half-word lane subscripting.
def VecListThreeDHWordIndexAsmOperand : AsmOperandClass {
let Name = "VecListThreeDHWordIndexed";
let ParserMethod = "parseVectorList";
let RenderMethod = "addVecListIndexedOperands";
}
def VecListThreeDHWordIndexed : Operand<i32> {
let ParserMatchClass = VecListThreeDHWordIndexAsmOperand;
let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
}
// ...with word lane subscripting.
def VecListThreeDWordIndexAsmOperand : AsmOperandClass {
let Name = "VecListThreeDWordIndexed";
let ParserMethod = "parseVectorList";
let RenderMethod = "addVecListIndexedOperands";
}
def VecListThreeDWordIndexed : Operand<i32> {
let ParserMatchClass = VecListThreeDWordIndexAsmOperand;
let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
}
// Register list of three Q registers with half-word lane subscripting.
def VecListThreeQHWordIndexAsmOperand : AsmOperandClass {
let Name = "VecListThreeQHWordIndexed";
let ParserMethod = "parseVectorList";
let RenderMethod = "addVecListIndexedOperands";
}
def VecListThreeQHWordIndexed : Operand<i32> {
let ParserMatchClass = VecListThreeQHWordIndexAsmOperand;
let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
}
// ...with word lane subscripting.
def VecListThreeQWordIndexAsmOperand : AsmOperandClass {
let Name = "VecListThreeQWordIndexed";
let ParserMethod = "parseVectorList";
let RenderMethod = "addVecListIndexedOperands";
}
def VecListThreeQWordIndexed : Operand<i32> {
let ParserMatchClass = VecListThreeQWordIndexAsmOperand;
let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// NEON-specific DAG Nodes. // NEON-specific DAG Nodes.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@ -5914,6 +5968,55 @@ def VST2LNqWB_register_Asm_32 :
rGPR:$Rm, pred:$p)>; rGPR:$Rm, pred:$p)>;
// VLD3 single-lane pseudo-instructions. These need special handling for
// the lane index that an InstAlias can't handle, so we use these instead.
def VLD3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
(ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
def VLD3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
(ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
def VLD3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
(ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
def VLD3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
(ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
def VLD3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
(ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
def VLD3LNdWB_fixed_Asm_8 :
NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
(ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
def VLD3LNdWB_fixed_Asm_16 :
NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
(ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
def VLD3LNdWB_fixed_Asm_32 :
NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
(ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
def VLD3LNqWB_fixed_Asm_16 :
NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
(ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
def VLD3LNqWB_fixed_Asm_32 :
NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
(ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
def VLD3LNdWB_register_Asm_8 :
NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
(ins VecListThreeDByteIndexed:$list, addrmode6:$addr,
rGPR:$Rm, pred:$p)>;
def VLD3LNdWB_register_Asm_16 :
NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
(ins VecListThreeDHWordIndexed:$list, addrmode6:$addr,
rGPR:$Rm, pred:$p)>;
def VLD3LNdWB_register_Asm_32 :
NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
(ins VecListThreeDWordIndexed:$list, addrmode6:$addr,
rGPR:$Rm, pred:$p)>;
def VLD3LNqWB_register_Asm_16 :
NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
(ins VecListThreeQHWordIndexed:$list, addrmode6:$addr,
rGPR:$Rm, pred:$p)>;
def VLD3LNqWB_register_Asm_32 :
NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
(ins VecListThreeQWordIndexed:$list, addrmode6:$addr,
rGPR:$Rm, pred:$p)>;
// VMOV takes an optional datatype suffix // VMOV takes an optional datatype suffix
defm : VFPDTAnyInstAlias<"vmov${p}", "$Vd, $Vm", defm : VFPDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
(VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>; (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;

164
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -1168,6 +1168,31 @@ public:
return VectorList.Count == 2 && VectorList.LaneIndex <= 1; return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
} }
bool isVecListThreeDByteIndexed() const {
if (!isSingleSpacedVectorIndexed()) return false;
return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
}
bool isVecListThreeDHWordIndexed() const {
if (!isSingleSpacedVectorIndexed()) return false;
return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
}
bool isVecListThreeQWordIndexed() const {
if (!isDoubleSpacedVectorIndexed()) return false;
return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
}
bool isVecListThreeQHWordIndexed() const {
if (!isDoubleSpacedVectorIndexed()) return false;
return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
}
bool isVecListThreeDWordIndexed() const {
if (!isSingleSpacedVectorIndexed()) return false;
return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
}
bool isVectorIndex8() const { bool isVectorIndex8() const {
if (Kind != k_VectorIndex) return false; if (Kind != k_VectorIndex) return false;
return VectorIndex.Val < 8; return VectorIndex.Val < 8;
@ -5304,6 +5329,53 @@ static unsigned getRealVLDLNOpcode(unsigned Opc, unsigned &Spacing) {
case ARM::VLD2LNqAsm_32: case ARM::VLD2LNqAsm_32:
Spacing = 2; Spacing = 2;
return ARM::VLD2LNq32; return ARM::VLD2LNq32;
// VLD3LN
case ARM::VLD3LNdWB_fixed_Asm_8:
Spacing = 1;
return ARM::VLD3LNd8_UPD;
case ARM::VLD3LNdWB_fixed_Asm_16:
Spacing = 1;
return ARM::VLD3LNd16_UPD;
case ARM::VLD3LNdWB_fixed_Asm_32:
Spacing = 1;
return ARM::VLD3LNd32_UPD;
case ARM::VLD3LNqWB_fixed_Asm_16:
Spacing = 1;
return ARM::VLD3LNq16_UPD;
case ARM::VLD3LNqWB_fixed_Asm_32:
Spacing = 2;
return ARM::VLD3LNq32_UPD;
case ARM::VLD3LNdWB_register_Asm_8:
Spacing = 1;
return ARM::VLD3LNd8_UPD;
case ARM::VLD3LNdWB_register_Asm_16:
Spacing = 1;
return ARM::VLD3LNd16_UPD;
case ARM::VLD3LNdWB_register_Asm_32:
Spacing = 1;
return ARM::VLD3LNd32_UPD;
case ARM::VLD3LNqWB_register_Asm_16:
Spacing = 2;
return ARM::VLD3LNq16_UPD;
case ARM::VLD3LNqWB_register_Asm_32:
Spacing = 2;
return ARM::VLD3LNq32_UPD;
case ARM::VLD3LNdAsm_8:
Spacing = 1;
return ARM::VLD3LNd8;
case ARM::VLD3LNdAsm_16:
Spacing = 1;
return ARM::VLD3LNd16;
case ARM::VLD3LNdAsm_32:
Spacing = 1;
return ARM::VLD3LNd32;
case ARM::VLD3LNqAsm_16:
Spacing = 2;
return ARM::VLD3LNq16;
case ARM::VLD3LNqAsm_32:
Spacing = 2;
return ARM::VLD3LNq32;
} }
} }
@ -5502,6 +5574,37 @@ processInstruction(MCInst &Inst,
return true; return true;
} }
case ARM::VLD3LNdWB_register_Asm_8:
case ARM::VLD3LNdWB_register_Asm_16:
case ARM::VLD3LNdWB_register_Asm_32:
case ARM::VLD3LNqWB_register_Asm_16:
case ARM::VLD3LNqWB_register_Asm_32: {
MCInst TmpInst;
// Shuffle the operands around so the lane index operand is in the
// right place.
unsigned Spacing;
TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
Spacing));
TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
Spacing));
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(4)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
Spacing));
TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
Spacing));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(5)); // CondCode
TmpInst.addOperand(Inst.getOperand(6));
Inst = TmpInst;
return true;
}
case ARM::VLD1LNdWB_fixed_Asm_8: case ARM::VLD1LNdWB_fixed_Asm_8:
case ARM::VLD1LNdWB_fixed_Asm_16: case ARM::VLD1LNdWB_fixed_Asm_16:
case ARM::VLD1LNdWB_fixed_Asm_32: { case ARM::VLD1LNdWB_fixed_Asm_32: {
@ -5550,6 +5653,37 @@ processInstruction(MCInst &Inst,
return true; return true;
} }
case ARM::VLD3LNdWB_fixed_Asm_8:
case ARM::VLD3LNdWB_fixed_Asm_16:
case ARM::VLD3LNdWB_fixed_Asm_32:
case ARM::VLD3LNqWB_fixed_Asm_16:
case ARM::VLD3LNqWB_fixed_Asm_32: {
MCInst TmpInst;
// Shuffle the operands around so the lane index operand is in the
// right place.
unsigned Spacing;
TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
Spacing));
TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
Spacing));
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
Spacing));
TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
Spacing));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
TmpInst.addOperand(Inst.getOperand(5));
Inst = TmpInst;
return true;
}
case ARM::VLD1LNdAsm_8: case ARM::VLD1LNdAsm_8:
case ARM::VLD1LNdAsm_16: case ARM::VLD1LNdAsm_16:
case ARM::VLD1LNdAsm_32: { case ARM::VLD1LNdAsm_32: {
@ -5593,6 +5727,36 @@ processInstruction(MCInst &Inst,
Inst = TmpInst; Inst = TmpInst;
return true; return true;
} }
case ARM::VLD3LNdAsm_8:
case ARM::VLD3LNdAsm_16:
case ARM::VLD3LNdAsm_32:
case ARM::VLD3LNqAsm_16:
case ARM::VLD3LNqAsm_32: {
MCInst TmpInst;
// Shuffle the operands around so the lane index operand is in the
// right place.
unsigned Spacing;
TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
Spacing));
TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
Spacing));
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
Spacing));
TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
Spacing));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
TmpInst.addOperand(Inst.getOperand(5));
Inst = TmpInst;
return true;
}
// Handle the Thumb2 mode MOV complex aliases. // Handle the Thumb2 mode MOV complex aliases.
case ARM::t2MOVsr: case ARM::t2MOVsr:
case ARM::t2MOVSsr: { case ARM::t2MOVSsr: {

42
llvm/test/MC/ARM/neon-vst-encoding.s
View File

@ -133,17 +133,39 @@
@ CHECK: vst2.32 {d5[0], d7[0]}, [r4, :64], r7 @ encoding: [0x57,0x59,0x84,0xf4] @ CHECK: vst2.32 {d5[0], d7[0]}, [r4, :64], r7 @ encoding: [0x57,0x59,0x84,0xf4]
@ vst3.8 {d16[1], d17[1], d18[1]}, [r0] vld3.8 {d16[1], d17[1], d18[1]}, [r1]
@ vst3.16 {d16[1], d17[1], d18[1]}, [r0] vld3.16 {d6[1], d7[1], d8[1]}, [r2]
@ vst3.32 {d16[1], d17[1], d18[1]}, [r0] vld3.32 {d1[1], d2[1], d3[1]}, [r3]
@ vst3.16 {d17[2], d19[2], d21[2]}, [r0] vld3.u16 {d27[2], d29[2], d31[2]}, [r4]
@ vst3.32 {d16[0], d18[0], d20[0]}, [r0] vld3.i32 {d6[0], d8[0], d10[0]}, [r5]
@ FIXME: vst3.8 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x2f,0x02,0xc0,0xf4] vld3.i8 {d12[3], d13[3], d14[3]}, [r6], r1
@ FIXME: vst3.16 {d16[1], d17[1], d18[1]}, [r0]@ encoding: [0x4f,0x06,0xc0,0xf4] vld3.i16 {d11[2], d12[2], d13[2]}, [r7], r2
@ FIXME: vst3.32 {d16[1], d17[1], d18[1]}, [r0]@ encoding: [0x8f,0x0a,0xc0,0xf4] vld3.u32 {d2[1], d3[1], d4[1]}, [r8], r3
@ FIXME: vst3.16 {d17[2], d19[2], d21[2]}, [r0]@ encoding: [0xaf,0x16,0xc0,0xf4] vld3.u16 {d14[2], d16[2], d18[2]}, [r9], r4
@ FIXME: vst3.32 {d16[0], d18[0], d20[0]}, [r0]@ encoding: [0x4f,0x0a,0xc0,0xf4] vld3.i32 {d16[0], d18[0], d20[0]}, [r10], r5
vld3.p8 {d6[6], d7[6], d8[6]}, [r8]!
vld3.16 {d9[2], d10[2], d11[2]}, [r7]!
vld3.f32 {d1[1], d2[1], d3[1]}, [r6]!
vld3.p16 {d20[2], d22[2], d24[2]}, [r5]!
vld3.32 {d5[0], d7[0], d9[0]}, [r4]!
@ CHECK: vld3.8 {d16[1], d17[1], d17[1]}, [r1] @ encoding: [0x2f,0x02,0xe1,0xf4]
@ CHECK: vld3.16 {d6[1], d7[1], d7[1]}, [r2] @ encoding: [0x4f,0x66,0xa2,0xf4]
@ CHECK: vld3.32 {d1[1], d2[1], d2[1]}, [r3] @ encoding: [0x8f,0x1a,0xa3,0xf4]
@ CHECK: vld3.16 {d27[2], d29[2], d29[2]}, [r4] @ encoding: [0xaf,0xb6,0xe4,0xf4]
@ CHECK: vld3.32 {d6[0], d8[0], d8[0]}, [r5] @ encoding: [0x4f,0x6a,0xa5,0xf4]
@ CHECK: vld3.8 {d12[3], d13[3], d13[3]}, [r6], r1 @ encoding: [0x61,0xc2,0xa6,0xf4]
@ CHECK: vld3.16 {d11[2], d12[2], d12[2]}, [r7], r2 @ encoding: [0x82,0xb6,0xa7,0xf4]
@ CHECK: vld3.32 {d2[1], d3[1], d3[1]}, [r8], r3 @ encoding: [0x83,0x2a,0xa8,0xf4]
@ CHECK: vld3.16 {d14[2], d16[2], d16[2]}, [r9], r4 @ encoding: [0xa4,0xe6,0xa9,0xf4]
@ CHECK: vld3.32 {d16[0], d18[0], d18[0]}, [r10], r5 @ encoding: [0x45,0x0a,0xea,0xf4]
@ CHECK: vld3.8 {d6[6], d7[6], d7[6]}, [r8]! @ encoding: [0xcd,0x62,0xa8,0xf4]
@ CHECK: vld3.16 {d9[2], d10[2], d10[2]}, [r7]! @ encoding: [0x8d,0x96,0xa7,0xf4]
@ CHECK: vld3.32 {d1[1], d2[1], d2[1]}, [r6]! @ encoding: [0x8d,0x1a,0xa6,0xf4]
@ CHECK: vld3.16 {d20[2], d21[2], d21[2]}, [r5]! @ encoding: [0xad,0x46,0xe5,0xf4]
@ CHECK: vld3.32 {d5[0], d7[0], d7[0]}, [r4]! @ encoding: [0x4d,0x5a,0xa4,0xf4]
@ vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] @ vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32]