AArch64: add newline to end of test files.

Should be no other change.

llvm-svn: 206174

llvm/test/CodeGen/AArch64/neon-add-pairwise.ll

@@ -98,4 +98,4 @@ define i32 @test_vaddv.v2i32(<2 x i32> %a) {
   ret i32 %2
 }
 
-declare <1 x i32> @llvm.aarch64.neon.vaddv.v1i32.v2i32(<2 x i32>)
+declare <1 x i32> @llvm.aarch64.neon.vaddv.v1i32.v2i32(<2 x i32>)

llvm/test/CodeGen/AArch64/neon-add-sub.ll

@@ -276,4 +276,4 @@ define <1 x i32> @test_sub_v1i32(<1 x i32> %a, <1 x i32> %b) {
 ;CHECK: sub {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
   %c = sub <1 x i32> %a, %b
   ret <1 x i32> %c
-}
+}

llvm/test/CodeGen/AArch64/neon-copyPhysReg-tuple.ll

@@ -44,4 +44,4 @@ entry:
 
 declare { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2lane.v4i32(i8*, <4 x i32>, <4 x i32>, i32, i32)
 declare { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld3lane.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32)
-declare { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld4lane.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32)
+declare { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld4lane.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32)

llvm/test/CodeGen/AArch64/neon-diagnostics.ll

@@ -21,4 +21,4 @@ define <4 x i32> @test_vshrn_not_match(<2 x i32> %a, <2 x i64> %b) {
   %shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %3, <2 x i32> <i32 0, i32 1>
   %4 = bitcast <2 x i64> %shuffle.i to <4 x i32>
   ret <4 x i32> %4
-}
+}

llvm/test/CodeGen/AArch64/neon-max-min-pairwise.ll

@@ -343,4 +343,4 @@ define i32 @test_vmaxv_u32(<2 x i32> %a) {
 declare <1 x i32> @llvm.aarch64.neon.uminv.v1i32.v2i32(<2 x i32>)
 declare <1 x i32> @llvm.aarch64.neon.sminv.v1i32.v2i32(<2 x i32>)
 declare <1 x i32> @llvm.aarch64.neon.umaxv.v1i32.v2i32(<2 x i32>)
-declare <1 x i32> @llvm.aarch64.neon.smaxv.v1i32.v2i32(<2 x i32>)
+declare <1 x i32> @llvm.aarch64.neon.smaxv.v1i32.v2i32(<2 x i32>)

llvm/test/CodeGen/AArch64/neon-misc.ll

@@ -2011,4 +2011,4 @@ define i64 @test_vaddlv_u32(<2 x i32> %a) {
 }
 
 declare <1 x i64> @llvm.aarch64.neon.saddlv.v1i64.v2i32(<2 x i32>)
-declare <1 x i64> @llvm.aarch64.neon.uaddlv.v1i64.v2i32(<2 x i32>)
+declare <1 x i64> @llvm.aarch64.neon.uaddlv.v1i64.v2i32(<2 x i32>)

llvm/test/CodeGen/AArch64/neon-scalar-neg.ll

@@ -58,4 +58,4 @@ entry:
   ret i64 %0
 }
 
-declare <1 x i64> @llvm.arm.neon.vqneg.v1i64(<1 x i64>)
+declare <1 x i64> @llvm.arm.neon.vqneg.v1i64(<1 x i64>)

llvm/test/CodeGen/AArch64/neon-simd-shift.ll

@@ -1553,4 +1553,4 @@ define <1 x double> @test_vcvt_n_f64_u64(<1 x i64> %a) {
 declare <1 x i64> @llvm.arm.neon.vcvtfp2fxs.v1i64.v1f64(<1 x double>, i32)
 declare <1 x i64> @llvm.arm.neon.vcvtfp2fxu.v1i64.v1f64(<1 x double>, i32)
 declare <1 x double> @llvm.arm.neon.vcvtfxs2fp.v1f64.v1i64(<1 x i64>, i32)
-declare <1 x double> @llvm.arm.neon.vcvtfxu2fp.v1f64.v1i64(<1 x i64>, i32)
+declare <1 x double> @llvm.arm.neon.vcvtfxu2fp.v1f64.v1i64(<1 x i64>, i32)

llvm/test/CodeGen/AArch64/neon-spill-fpr8-fpr16.ll

@@ -27,4 +27,4 @@ define void @spill_fpr16(%bigtype_v1i16* %addr) {
   store volatile %bigtype_v1i16 %val1, %bigtype_v1i16* %addr
   store volatile %bigtype_v1i16 %val2, %bigtype_v1i16* %addr
   ret void
-}
+}

llvm/test/CodeGen/AArch64/neon-truncStore-extLoad.ll

@@ -54,4 +54,4 @@ define i32 @loadExt.i32(<4 x i8>* %ref) {
   %vecext = extractelement <4 x i8> %a, i32 0
   %conv = zext i8 %vecext to i32
   ret i32 %conv
-}
+}

llvm/test/CodeGen/AArch64/neon-vector-list-spill.ll

@@ -172,4 +172,4 @@ define <8 x i16> @test_4xFPR128Lo(i64 %got, i8* %ptr, <1 x i64> %a) {
 
 declare void @llvm.arm.neon.vst2lane.v1i64(i8*, <1 x i64>, <1 x i64>, i32, i32)
 declare void @llvm.arm.neon.vst3lane.v1i64(i8*, <1 x i64>, <1 x i64>, <1 x i64>, i32, i32)
-declare void @llvm.arm.neon.vst4lane.v1i64(i8*, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, i32, i32)
+declare void @llvm.arm.neon.vst4lane.v1i64(i8*, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, i32, i32)