forked from OSchip/llvm-project
Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV.
llvm-svn: 139485
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@ -650,6 +650,15 @@ class BinOpRR_Rev<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo>
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let isCodeGenOnly = 1;
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}
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// BinOpRR_F_Rev - Instructions like "cmp reg, reg" (reversed encoding).
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class BinOpRR_F_Rev<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo>
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: ITy<opcode, MRMSrcReg, typeinfo, (outs),
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(ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
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mnemonic, "{$src2, $src1|$src1, $src2}", []> {
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// The disassembler should know about this, but not the asmparser.
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let isCodeGenOnly = 1;
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}
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// BinOpRM - Instructions like "add reg, reg, [mem]".
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class BinOpRM<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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dag outlist, list<dag> pattern>
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@ -1017,10 +1026,10 @@ multiclass ArithBinOp_F<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
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def #NAME#64rr : BinOpRR_F<BaseOpc, mnemonic, Xi64, opnode>;
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} // isCommutable
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def #NAME#8rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi8>;
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def #NAME#16rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi16>;
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def #NAME#32rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi32>;
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def #NAME#64rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi64>;
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def #NAME#8rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi8>;
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def #NAME#16rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi16>;
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def #NAME#32rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi32>;
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def #NAME#64rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi64>;
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def #NAME#8rm : BinOpRM_F<BaseOpc2, mnemonic, Xi8 , opnode>;
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def #NAME#16rm : BinOpRM_F<BaseOpc2, mnemonic, Xi16, opnode>;
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@ -161,3 +161,15 @@
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# CHECK: pause
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0xf3 0x90
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# CHECK: addl %eax, %edi
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0x01 0xc7
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# CHECK: addl %edi, %eax
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0x03 0xc7
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# CHECK: movl %eax, %edi
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0x89 0xc7
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# CHECK: movl %edi, %eax
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0x8b 0xc7
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@ -345,7 +345,7 @@ RecognizableInstr::filter_ret RecognizableInstr::filter() const {
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return FILTER_STRONG;
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if (Form == X86Local::Pseudo ||
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IsCodeGenOnly)
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(IsCodeGenOnly && Name.find("_REV") == Name.npos))
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return FILTER_STRONG;
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if (Form == X86Local::MRMInitReg)
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