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[mips][microMIPS] Fix issue with offset operand of BALC and BC instructions 

Value of offset operand for microMIPS BALC and BC instructions is currently shifted 2 bits, but it should be 1 bit.
Differential Revision: http://reviews.llvm.org/D14770

llvm-svn: 254296
This commit is contained in:
Zoran Jovanovic 2015-11-30 12:56:18 +00:00
parent ea7932cfb7
commit a887b36167
6 changed files with 54 additions and 6 deletions
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17
llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
View File

@ -229,6 +229,13 @@ static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
uint64_t Address,
const void *Decoder);
// DecodeBranchTarget26MM - Decode microMIPS branch offset, which is
// shifted left by 1 bit.
static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst,
unsigned Offset,
uint64_t Address,
const void *Decoder);
// DecodeJumpTargetMM - Decode microMIPS jump target, which is
// shifted left by 1 bit.
static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
@ -1863,6 +1870,16 @@ static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
return MCDisassembler::Success;
}
static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst,
unsigned Offset,
uint64_t Address,
const void *Decoder) {
int32_t BranchOffset = SignExtend32<26>(Offset) << 1;
Inst.addOperand(MCOperand::createImm(BranchOffset));
return MCDisassembler::Success;
}
static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
unsigned Insn,
uint64_t Address,

17
llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
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@ -350,6 +350,23 @@ getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
return 0;
}
/// getBranchTarget26OpValueMM - Return binary encoding of the branch
/// target operand. If the machine operand requires relocation,
/// record the relocation and return zero.
unsigned MipsMCCodeEmitter::getBranchTarget26OpValueMM(
const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo);
// If the destination is an immediate, divide by 2.
if (MO.isImm())
return MO.getImm() >> 1;
// TODO: Push 26 PC fixup.
return 0;
}
/// getJumpOffset16OpValue - Return binary encoding of the jump
/// target operand. If the machine operand requires relocation,
/// record the relocation and return zero.

7
llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
View File

@ -137,6 +137,13 @@ public:
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
// getBranchTarget26OpValueMM - Return binary encoding of the branch
// offset operand. If the machine operand requires relocation,
// record the relocation and return zero.
unsigned getBranchTarget26OpValueMM(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
// getJumpOffset16OpValue - Return binary encoding of the jump
// offset operand. If the machine operand requires relocation,
// record the relocation and return zero.

11
llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
View File

@ -11,6 +11,13 @@
//
//===----------------------------------------------------------------------===//
def brtarget26_mm : Operand<OtherVT> {
let EncoderMethod = "getBranchTarget26OpValueMM";
let OperandType = "OPERAND_PCREL";
let DecoderMethod = "DecodeBranchTarget26MM";
let ParserMatchClass = MipsJumpTargetAsmOperand;
}
//===----------------------------------------------------------------------===//
//
// Instruction Encodings
@ -238,11 +245,11 @@ class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd>
bit isBarrier = 1;
}
class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26> {
class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26_mm> {
bit isCall = 1;
list<Register> Defs = [RA];
}
class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26>;
class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26_mm>;
class BC16_MMR6_DESC : MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
!strconcat("bc16", "\t$offset"), [],

4
llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt
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@ -44,8 +44,8 @@
0xe0 0x40 0x02 0x9a # CHECK: bgtzalc $2, 1332
0xe0 0x42 0x02 0x9a # CHECK: bltzalc $2, 1332
0xc0 0x40 0x02 0x9a # CHECK: blezalc $2, 1332
0xb4 0x37 0x96 0xb8 # CHECK: balc 14572256
0x94 0x37 0x96 0xb8 # CHECK: bc 14572256
0xb4 0x37 0x96 0xb8 # CHECK: balc 7286128
0x94 0x37 0x96 0xb8 # CHECK: bc 7286128
0x00 0x44 0x0b 0x3c # CHECK: bitswap $4, $2
0x00 0x00 0x00 0x07 # CHECK: break
0x00 0x07 0x00 0x07 # CHECK: break 7

4
llvm/test/MC/Mips/micromips32r6/valid.s
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@ -26,9 +26,9 @@
bgtzalc $2, 1332 # CHECK: bgtzalc $2, 1332 # encoding: [0xe0,0x40,0x02,0x9a]
bltzalc $2, 1332 # CHECK: bltzalc $2, 1332 # encoding: [0xe0,0x42,0x02,0x9a]
blezalc $2, 1332 # CHECK: blezalc $2, 1332 # encoding: [0xc0,0x40,0x02,0x9a]
balc 14572256 # CHECK: balc 14572256 # encoding: [0xb4,0x37,0x96,0xb8]
balc 7286128 # CHECK: balc 7286128 # encoding: [0xb4,0x37,0x96,0xb8]
b 132 # CHECK: bc16 132 # encoding: [0xcc,0x42]
bc 14572256 # CHECK: bc 14572256 # encoding: [0x94,0x37,0x96,0xb8]
bc 7286128 # CHECK: bc 7286128 # encoding: [0x94,0x37,0x96,0xb8]
bc16 132 # CHECK: bc16 132 # encoding: [0xcc,0x42]
beqzc16 $6, 20 # CHECK: beqzc16 $6, 20 # encoding: [0x8f,0x0a]
bnezc16 $6, 20 # CHECK: bnezc16 $6, 20 # encoding: [0xaf,0x0a]