forked from OSchip/llvm-project
parent
dfad8ed54e
commit
a87d743912
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@ -1124,22 +1124,23 @@ void DAGISelEmitter::ParseInstructions() {
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CodeGenInstruction &InstInfo =Target.getInstruction(Instrs[i]->getName());
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// Note: Removed if (InstInfo.OperandList.size() == 0) continue;
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// It's possible for some instruction, e.g. RET for X86 that only has an
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// implicit flag operand.
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// FIXME: temporary hack...
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if (InstInfo.isReturn || InstInfo.isBranch || InstInfo.isCall ||
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InstInfo.isStore) {
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// These produce no results
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for (unsigned j = 0, e = InstInfo.OperandList.size(); j < e; ++j)
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Operands.push_back(InstInfo.OperandList[j].Rec);
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} else {
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// Assume the first operand is the result.
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Results.push_back(InstInfo.OperandList[0].Rec);
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if (InstInfo.OperandList.size() != 0) {
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// It's possible for some instruction, e.g. RET for X86 that only has an
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// implicit flag operand.
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// FIXME: temporary hack...
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if (InstInfo.isReturn || InstInfo.isBranch || InstInfo.isCall ||
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InstInfo.isStore) {
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// These produce no results
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for (unsigned j = 0, e = InstInfo.OperandList.size(); j < e; ++j)
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Operands.push_back(InstInfo.OperandList[j].Rec);
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} else {
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// Assume the first operand is the result.
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Results.push_back(InstInfo.OperandList[0].Rec);
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// The rest are inputs.
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for (unsigned j = 1, e = InstInfo.OperandList.size(); j < e; ++j)
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Operands.push_back(InstInfo.OperandList[j].Rec);
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// The rest are inputs.
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for (unsigned j = 1, e = InstInfo.OperandList.size(); j < e; ++j)
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Operands.push_back(InstInfo.OperandList[j].Rec);
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}
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}
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// Create and insert the instruction.
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