forked from OSchip/llvm-project
[X86] Extract PSIGN/BLENDVP tests into vector-blend.ll. NFC.
We're going to stop generating PSIGN, so calling a test "psign" isn't ideal. Instead, call these tests what they really are: variable blends using logic. Also add a test to exhibit a case we're currently missing in the PSIGN combine. llvm-svn: 261022
This commit is contained in:
Ahmed Bougacha
parent
f211f685e4
commit
a87c3480b5
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@ -53,35 +53,6 @@ define <32 x i8> @vpblendvb(<32 x i1> %cond, <32 x i8> %x, <32 x i8> %y) {
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ret <32 x i8> %min
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}
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define <8 x i32> @signd(<8 x i32> %a, <8 x i32> %b) nounwind {
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entry:
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; CHECK-LABEL: signd:
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; CHECK: psignd
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; CHECK-NOT: sub
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; CHECK: ret
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%b.lobit = ashr <8 x i32> %b, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
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%sub = sub nsw <8 x i32> zeroinitializer, %a
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%0 = xor <8 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
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%1 = and <8 x i32> %a, %0
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%2 = and <8 x i32> %b.lobit, %sub
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%cond = or <8 x i32> %1, %2
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ret <8 x i32> %cond
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}
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define <8 x i32> @blendvb(<8 x i32> %b, <8 x i32> %a, <8 x i32> %c) nounwind {
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entry:
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; CHECK-LABEL: blendvb:
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; CHECK: pblendvb
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; CHECK: ret
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%b.lobit = ashr <8 x i32> %b, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
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%sub = sub nsw <8 x i32> zeroinitializer, %a
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%0 = xor <8 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
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%1 = and <8 x i32> %c, %0
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%2 = and <8 x i32> %a, %b.lobit
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%cond = or <8 x i32> %1, %2
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ret <8 x i32> %cond
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}
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define <8 x i32> @allOnes() nounwind {
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; CHECK: vpcmpeqd
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; CHECK-NOT: vinsert
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@ -1,30 +0,0 @@
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; RUN: llc < %s -march=x86 -mcpu=nehalem | FileCheck %s
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define <4 x i32> @signd(<4 x i32> %a, <4 x i32> %b) nounwind {
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entry:
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; CHECK-LABEL: signd:
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; CHECK: psignd
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; CHECK-NOT: sub
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; CHECK: ret
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%b.lobit = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
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%sub = sub nsw <4 x i32> zeroinitializer, %a
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%0 = xor <4 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1>
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%1 = and <4 x i32> %a, %0
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%2 = and <4 x i32> %b.lobit, %sub
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%cond = or <4 x i32> %1, %2
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ret <4 x i32> %cond
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}
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define <4 x i32> @blendvb(<4 x i32> %b, <4 x i32> %a, <4 x i32> %c) nounwind {
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entry:
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; CHECK-LABEL: blendvb:
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; CHECK: pblendvb
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; CHECK: ret
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%b.lobit = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
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%sub = sub nsw <4 x i32> zeroinitializer, %a
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%0 = xor <4 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1>
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%1 = and <4 x i32> %c, %0
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%2 = and <4 x i32> %a, %b.lobit
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%cond = or <4 x i32> %1, %2
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ret <4 x i32> %cond
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}
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@ -802,3 +802,254 @@ entry:
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%select = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
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ret <4 x i64> %select
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}
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define <4 x i32> @blend_logic_v4i32(<4 x i32> %b, <4 x i32> %a, <4 x i32> %c) {
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; SSE2-LABEL: blend_logic_v4i32:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: psrad $31, %xmm0
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; SSE2-NEXT: pand %xmm0, %xmm1
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; SSE2-NEXT: pandn %xmm2, %xmm0
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; SSE2-NEXT: por %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: blend_logic_v4i32:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: psrad $31, %xmm0
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; SSSE3-NEXT: pand %xmm0, %xmm1
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; SSSE3-NEXT: pandn %xmm2, %xmm0
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; SSSE3-NEXT: por %xmm1, %xmm0
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: blend_logic_v4i32:
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; SSE41: # BB#0: # %entry
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; SSE41-NEXT: psrad $31, %xmm0
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; SSE41-NEXT: pblendvb %xmm1, %xmm2
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; SSE41-NEXT: movdqa %xmm2, %xmm0
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: blend_logic_v4i32:
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vpsrad $31, %xmm0, %xmm0
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; AVX-NEXT: vpblendvb %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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entry:
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%b.lobit = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
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%sub = sub nsw <4 x i32> zeroinitializer, %a
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%0 = xor <4 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1>
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%1 = and <4 x i32> %c, %0
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%2 = and <4 x i32> %a, %b.lobit
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%cond = or <4 x i32> %1, %2
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ret <4 x i32> %cond
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}
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define <8 x i32> @blend_logic_v8i32(<8 x i32> %b, <8 x i32> %a, <8 x i32> %c) {
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; SSE2-LABEL: blend_logic_v8i32:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: psrad $31, %xmm0
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; SSE2-NEXT: psrad $31, %xmm1
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; SSE2-NEXT: pand %xmm1, %xmm3
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; SSE2-NEXT: pandn %xmm5, %xmm1
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; SSE2-NEXT: pand %xmm0, %xmm2
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; SSE2-NEXT: pandn %xmm4, %xmm0
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; SSE2-NEXT: por %xmm2, %xmm0
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; SSE2-NEXT: por %xmm3, %xmm1
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: blend_logic_v8i32:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: psrad $31, %xmm0
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; SSSE3-NEXT: psrad $31, %xmm1
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; SSSE3-NEXT: pand %xmm1, %xmm3
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; SSSE3-NEXT: pandn %xmm5, %xmm1
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; SSSE3-NEXT: pand %xmm0, %xmm2
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; SSSE3-NEXT: pandn %xmm4, %xmm0
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; SSSE3-NEXT: por %xmm2, %xmm0
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; SSSE3-NEXT: por %xmm3, %xmm1
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: blend_logic_v8i32:
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; SSE41: # BB#0: # %entry
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; SSE41-NEXT: psrad $31, %xmm1
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; SSE41-NEXT: psrad $31, %xmm0
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; SSE41-NEXT: pblendvb %xmm2, %xmm4
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; SSE41-NEXT: movdqa %xmm1, %xmm0
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; SSE41-NEXT: pblendvb %xmm3, %xmm5
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; SSE41-NEXT: movdqa %xmm4, %xmm0
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; SSE41-NEXT: movdqa %xmm5, %xmm1
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; SSE41-NEXT: retq
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;
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; AVX1-LABEL: blend_logic_v8i32:
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; AVX1: # BB#0: # %entry
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; AVX1-NEXT: vpsrad $31, %xmm0, %xmm3
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
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; AVX1-NEXT: vpsrad $31, %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm3, %ymm0
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; AVX1-NEXT: vandnps %ymm2, %ymm0, %ymm2
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; AVX1-NEXT: vandps %ymm0, %ymm1, %ymm0
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; AVX1-NEXT: vorps %ymm0, %ymm2, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: blend_logic_v8i32:
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; AVX2: # BB#0: # %entry
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; AVX2-NEXT: vpsrad $31, %ymm0, %ymm0
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; AVX2-NEXT: vpblendvb %ymm0, %ymm1, %ymm2, %ymm0
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; AVX2-NEXT: retq
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entry:
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%b.lobit = ashr <8 x i32> %b, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
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%sub = sub nsw <8 x i32> zeroinitializer, %a
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%0 = xor <8 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
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%1 = and <8 x i32> %c, %0
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%2 = and <8 x i32> %a, %b.lobit
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%cond = or <8 x i32> %1, %2
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ret <8 x i32> %cond
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}
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define <4 x i32> @blend_neg_logic_v4i32(<4 x i32> %a, <4 x i32> %b) {
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; SSE2-LABEL: blend_neg_logic_v4i32:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: psrad $31, %xmm1
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; SSE2-NEXT: pxor %xmm2, %xmm2
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; SSE2-NEXT: psubd %xmm0, %xmm2
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; SSE2-NEXT: pand %xmm1, %xmm2
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; SSE2-NEXT: pandn %xmm0, %xmm1
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; SSE2-NEXT: por %xmm1, %xmm2
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; SSE2-NEXT: movdqa %xmm2, %xmm0
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: blend_neg_logic_v4i32:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: psignd %xmm1, %xmm0
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: blend_neg_logic_v4i32:
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; SSE41: # BB#0: # %entry
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; SSE41-NEXT: psignd %xmm1, %xmm0
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: blend_neg_logic_v4i32:
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vpsignd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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entry:
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%b.lobit = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
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%sub = sub nsw <4 x i32> zeroinitializer, %a
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%0 = xor <4 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1>
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%1 = and <4 x i32> %a, %0
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%2 = and <4 x i32> %b.lobit, %sub
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%cond = or <4 x i32> %1, %2
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ret <4 x i32> %cond
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}
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define <8 x i32> @blend_neg_logic_v8i32(<8 x i32> %a, <8 x i32> %b) {
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; SSE2-LABEL: blend_neg_logic_v8i32:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: psrad $31, %xmm2
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; SSE2-NEXT: psrad $31, %xmm3
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; SSE2-NEXT: pxor %xmm4, %xmm4
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; SSE2-NEXT: pxor %xmm5, %xmm5
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; SSE2-NEXT: psubd %xmm0, %xmm5
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; SSE2-NEXT: psubd %xmm1, %xmm4
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; SSE2-NEXT: pand %xmm3, %xmm4
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; SSE2-NEXT: pandn %xmm1, %xmm3
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; SSE2-NEXT: pand %xmm2, %xmm5
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; SSE2-NEXT: pandn %xmm0, %xmm2
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; SSE2-NEXT: por %xmm2, %xmm5
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; SSE2-NEXT: por %xmm3, %xmm4
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; SSE2-NEXT: movdqa %xmm5, %xmm0
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; SSE2-NEXT: movdqa %xmm4, %xmm1
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: blend_neg_logic_v8i32:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: psignd %xmm2, %xmm0
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; SSSE3-NEXT: psignd %xmm3, %xmm1
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: blend_neg_logic_v8i32:
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; SSE41: # BB#0: # %entry
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; SSE41-NEXT: psignd %xmm2, %xmm0
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; SSE41-NEXT: psignd %xmm3, %xmm1
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; SSE41-NEXT: retq
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;
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; AVX1-LABEL: blend_neg_logic_v8i32:
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; AVX1: # BB#0: # %entry
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; AVX1-NEXT: vpsrad $31, %xmm1, %xmm2
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; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
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; AVX1-NEXT: vpsrad $31, %xmm1, %xmm1
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
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; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; AVX1-NEXT: vpsubd %xmm2, %xmm3, %xmm2
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; AVX1-NEXT: vpsubd %xmm0, %xmm3, %xmm3
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; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2
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; AVX1-NEXT: vandnps %ymm0, %ymm1, %ymm0
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; AVX1-NEXT: vandps %ymm2, %ymm1, %ymm1
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; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: blend_neg_logic_v8i32:
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; AVX2: # BB#0: # %entry
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; AVX2-NEXT: vpsignd %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: retq
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entry:
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%b.lobit = ashr <8 x i32> %b, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
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%sub = sub nsw <8 x i32> zeroinitializer, %a
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%0 = xor <8 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
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%1 = and <8 x i32> %a, %0
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%2 = and <8 x i32> %b.lobit, %sub
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%cond = or <8 x i32> %1, %2
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ret <8 x i32> %cond
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}
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define <4 x i32> @blend_neg_logic_v4i32_2(<4 x i32> %v, <4 x i32> %c) {
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; SSE2-LABEL: blend_neg_logic_v4i32_2:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: psrld $31, %xmm1
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; SSE2-NEXT: pslld $31, %xmm1
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; SSE2-NEXT: psrad $31, %xmm1
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; SSE2-NEXT: pxor %xmm2, %xmm2
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; SSE2-NEXT: psubd %xmm0, %xmm2
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; SSE2-NEXT: pand %xmm1, %xmm0
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; SSE2-NEXT: pandn %xmm2, %xmm1
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; SSE2-NEXT: por %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: blend_neg_logic_v4i32_2:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: psrld $31, %xmm1
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; SSSE3-NEXT: pslld $31, %xmm1
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; SSSE3-NEXT: psrad $31, %xmm1
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; SSSE3-NEXT: pxor %xmm2, %xmm2
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; SSSE3-NEXT: psubd %xmm0, %xmm2
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; SSSE3-NEXT: pand %xmm1, %xmm0
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; SSSE3-NEXT: pandn %xmm2, %xmm1
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; SSSE3-NEXT: por %xmm1, %xmm0
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: blend_neg_logic_v4i32_2:
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; SSE41: # BB#0: # %entry
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; SSE41-NEXT: movdqa %xmm0, %xmm2
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; SSE41-NEXT: psrld $31, %xmm1
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; SSE41-NEXT: pslld $31, %xmm1
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; SSE41-NEXT: pxor %xmm3, %xmm3
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; SSE41-NEXT: psubd %xmm2, %xmm3
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; SSE41-NEXT: movdqa %xmm1, %xmm0
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; SSE41-NEXT: blendvps %xmm2, %xmm3
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; SSE41-NEXT: movaps %xmm3, %xmm0
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: blend_neg_logic_v4i32_2:
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vpsrld $31, %xmm1, %xmm1
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; AVX-NEXT: vpslld $31, %xmm1, %xmm1
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; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX-NEXT: vpsubd %xmm0, %xmm2, %xmm2
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; AVX-NEXT: vblendvps %xmm1, %xmm0, %xmm2, %xmm0
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; AVX-NEXT: retq
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entry:
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%0 = ashr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
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%1 = trunc <4 x i32> %0 to <4 x i1>
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%2 = sub nsw <4 x i32> zeroinitializer, %v
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%3 = select <4 x i1> %1, <4 x i32> %v, <4 x i32> %2
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ret <4 x i32> %3
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}
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