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[ARM] Add register-mask for tail returns 

The TC_RETURN/TCRETURNdi under Arm does not currently add the
register-mask operand when tail folding, which leads to the register
(like LR) not being 'used' by the return. This changes the code to
unconditionally set the register mask on the call, as opposed to
skipping it for tail calls.

I don't believe this will currently alter any codegen, but should glue
things together better post-frame lowering. It matches the AArch64 code
better.

Differential Revision: https://reviews.llvm.org/D125906
This commit is contained in:
David Green 2022-05-21 15:28:24 +01:00
parent c8b675eaa1
commit a86cfaea54
3 changed files with 17 additions and 19 deletions
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32
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -2786,25 +2786,23 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
RegsToPass[i].second.getValueType())); RegsToPass[i].second.getValueType()));
// Add a register mask operand representing the call-preserved registers. // Add a register mask operand representing the call-preserved registers.
if (!isTailCall) { const uint32_t *Mask;
const uint32_t *Mask; const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo(); if (isThisReturn) {
if (isThisReturn) { // For 'this' returns, use the R0-preserving mask if applicable
// For 'this' returns, use the R0-preserving mask if applicable Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
Mask = ARI->getThisReturnPreservedMask(MF, CallConv); if (!Mask) {
if (!Mask) { // Set isThisReturn to false if the calling convention is not one that
// Set isThisReturn to false if the calling convention is not one that // allows 'returned' to be modeled in this way, so LowerCallResult does
// allows 'returned' to be modeled in this way, so LowerCallResult does // not try to pass 'this' straight through
// not try to pass 'this' straight through isThisReturn = false;
isThisReturn = false;
Mask = ARI->getCallPreservedMask(MF, CallConv);
}
} else
Mask = ARI->getCallPreservedMask(MF, CallConv); Mask = ARI->getCallPreservedMask(MF, CallConv);
}
} else
Mask = ARI->getCallPreservedMask(MF, CallConv);
assert(Mask && "Missing call preserved mask for calling convention"); assert(Mask && "Missing call preserved mask for calling convention");
Ops.push_back(DAG.getRegisterMask(Mask)); Ops.push_back(DAG.getRegisterMask(Mask));
}
if (InFlag.getNode()) if (InFlag.getNode())
Ops.push_back(InFlag); Ops.push_back(InFlag);

2
llvm/test/CodeGen/ARM/dbg-tcreturn.ll
View File

@ -12,7 +12,7 @@ target triple = "thumbv7-apple-ios7.0.0"
; CHECK-NEXT: $r0 = COPY %0 ; CHECK-NEXT: $r0 = COPY %0
; CHECK-NEXT: $r1 = COPY %1 ; CHECK-NEXT: $r1 = COPY %1
; CHECK-NEXT: DBG_VALUE $noreg, $noreg, !13, !DIExpression(), debug-location !16 ; CHECK-NEXT: DBG_VALUE $noreg, $noreg, !13, !DIExpression(), debug-location !16
; CHECK-NEXT: TCRETURNdi &__divsi3, 0, implicit $sp, implicit $r0, implicit $r1 ; CHECK-NEXT: TCRETURNdi &__divsi3, 0, csr_ios, implicit $sp, implicit $r0, implicit $r1
define i32 @test(i32 %a1, i32 %a2) !dbg !5 { define i32 @test(i32 %a1, i32 %a2) !dbg !5 {
entry: entry:

2
llvm/test/DebugInfo/ARM/instr-ref-tcreturn.ll
View File

@ -26,7 +26,7 @@ target triple = "thumbv7-apple-ios7.0.0"
; CHECK: $r0 = COPY %0 ; CHECK: $r0 = COPY %0
; CHECK-NEXT: $r1 = COPY %1 ; CHECK-NEXT: $r1 = COPY %1
; CHECK-NEXT: DBG_INSTR_REF 1, 0 ; CHECK-NEXT: DBG_INSTR_REF 1, 0
; CHECK-NEXT: TCRETURNdi &__divsi3, 0, implicit $sp, implicit $r0, implicit $r1 ; CHECK-NEXT: TCRETURNdi &__divsi3, 0, csr_ios, implicit $sp, implicit $r0, implicit $r1
declare i1 @ext() declare i1 @ext()