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[X86][tablgen] Rename some fields for RecognizableInstrBase to align with fields in TD file. NFC 

The comment for `HasVEX_L` is updated.
This commit is contained in:
Shengchen Kan 2022-03-26 23:32:50 +08:00
parent dc68ca3eff
commit a86cd3be1c
4 changed files with 19 additions and 19 deletions
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4
llvm/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp
View File

@ -122,7 +122,7 @@ public:
// VEX/EVEX fields
VEXRI.OpPrefix != EVEXRI.OpPrefix || VEXRI.OpMap != EVEXRI.OpMap ||
VEXRI.HasVEX_4V != EVEXRI.HasVEX_4V ||
VEXRI.HasVEX_LPrefix != EVEXRI.HasVEX_LPrefix ||
VEXRI.HasVEX_L != EVEXRI.HasVEX_L ||
// Match is allowed if either is VEX_WIG, or they match, or EVEX
// is VEX_W1X and VEX is VEX_W0.
(!(VEX_WIG || (!EVEX_WIG && EVEX_W == VEX_W) ||
@ -217,7 +217,7 @@ void X86EVEX2VEXTablesEmitter::run(raw_ostream &OS) {
VEXInsts[RI.Opcode].push_back(Inst);
// Add relevant EVEX encoded instructions to EVEXInsts
else if (RI.Encoding == X86Local::EVEX && !RI.HasEVEX_K && !RI.HasEVEX_B &&
!RI.HasEVEX_L2Prefix && !Def->getValueAsBit("notEVEX2VEXConvertible"))
!RI.HasEVEX_L2 && !Def->getValueAsBit("notEVEX2VEXConvertible"))
EVEXInsts.push_back(Inst);
}

4
llvm/utils/TableGen/X86FoldTablesEmitter.cpp
View File

@ -330,13 +330,13 @@ public:
RegRI.OpSize != MemRI.OpSize || RegRI.AdSize != MemRI.AdSize ||
RegRI.HasREX_W != MemRI.HasREX_W ||
RegRI.HasVEX_4V != MemRI.HasVEX_4V ||
RegRI.HasVEX_LPrefix != MemRI.HasVEX_LPrefix ||
RegRI.HasVEX_L != MemRI.HasVEX_L ||
RegRI.HasVEX_W != MemRI.HasVEX_W ||
RegRI.IgnoresVEX_L != MemRI.IgnoresVEX_L ||
RegRI.IgnoresVEX_W != MemRI.IgnoresVEX_W ||
RegRI.HasEVEX_K != MemRI.HasEVEX_K ||
RegRI.HasEVEX_KZ != MemRI.HasEVEX_KZ ||
RegRI.HasEVEX_L2Prefix != MemRI.HasEVEX_L2Prefix ||
RegRI.HasEVEX_L2 != MemRI.HasEVEX_L2 ||
RegRec->getValueAsBit("hasEVEX_RC") !=
MemRec->getValueAsBit("hasEVEX_RC") ||
RegRec->getValueAsBit("hasLockPrefix") !=

24
llvm/utils/TableGen/X86RecognizableInstr.cpp
View File

@ -90,7 +90,7 @@ RecognizableInstrBase::RecognizableInstrBase(const CodeGenInstruction &insn) {
HasVEX_W = Rec->getValueAsBit("HasVEX_W");
IgnoresVEX_W = Rec->getValueAsBit("IgnoresVEX_W");
IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
HasEVEX_L2 = Rec->getValueAsBit("hasEVEX_L2");
HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
@ -98,7 +98,7 @@ RecognizableInstrBase::RecognizableInstrBase(const CodeGenInstruction &insn) {
IsAsmParserOnly = Rec->getValueAsBit("isAsmParserOnly");
ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
CD8_Scale = byteFromRec(Rec, "CD8_Scale");
HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
HasVEX_L = Rec->getValueAsBit("hasVEX_L");
EncodeRC = HasEVEX_B &&
(Form == X86Local::MRMDestReg || Form == X86Local::MRMSrcReg);
@ -153,12 +153,12 @@ InstructionContext RecognizableInstr::insnContext() const {
InstructionContext insnContext;
if (Encoding == X86Local::EVEX) {
if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
if (HasVEX_L && HasEVEX_L2) {
errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
}
// VEX_L & VEX_W
if (!EncodeRC && HasVEX_LPrefix && HasVEX_W) {
if (!EncodeRC && HasVEX_L && HasVEX_W) {
if (OpPrefix == X86Local::PD)
insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
else if (OpPrefix == X86Local::XS)
@ -171,7 +171,7 @@ InstructionContext RecognizableInstr::insnContext() const {
errs() << "Instruction does not use a prefix: " << Name << "\n";
llvm_unreachable("Invalid prefix");
}
} else if (!EncodeRC && HasVEX_LPrefix) {
} else if (!EncodeRC && HasVEX_L) {
// VEX_L
if (OpPrefix == X86Local::PD)
insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
@ -185,7 +185,7 @@ InstructionContext RecognizableInstr::insnContext() const {
errs() << "Instruction does not use a prefix: " << Name << "\n";
llvm_unreachable("Invalid prefix");
}
} else if (!EncodeRC && HasEVEX_L2Prefix && HasVEX_W) {
} else if (!EncodeRC && HasEVEX_L2 && HasVEX_W) {
// EVEX_L2 & VEX_W
if (OpPrefix == X86Local::PD)
insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
@ -199,7 +199,7 @@ InstructionContext RecognizableInstr::insnContext() const {
errs() << "Instruction does not use a prefix: " << Name << "\n";
llvm_unreachable("Invalid prefix");
}
} else if (!EncodeRC && HasEVEX_L2Prefix) {
} else if (!EncodeRC && HasEVEX_L2) {
// EVEX_L2
if (OpPrefix == X86Local::PD)
insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
@ -244,7 +244,7 @@ InstructionContext RecognizableInstr::insnContext() const {
}
/// eof EVEX
} else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) {
if (HasVEX_LPrefix && HasVEX_W) {
if (HasVEX_L && HasVEX_W) {
if (OpPrefix == X86Local::PD)
insnContext = IC_VEX_L_W_OPSIZE;
else if (OpPrefix == X86Local::XS)
@ -257,7 +257,7 @@ InstructionContext RecognizableInstr::insnContext() const {
errs() << "Instruction does not use a prefix: " << Name << "\n";
llvm_unreachable("Invalid prefix");
}
} else if (OpPrefix == X86Local::PD && HasVEX_LPrefix)
} else if (OpPrefix == X86Local::PD && HasVEX_L)
insnContext = IC_VEX_L_OPSIZE;
else if (OpPrefix == X86Local::PD && HasVEX_W)
insnContext = IC_VEX_W_OPSIZE;
@ -268,9 +268,9 @@ InstructionContext RecognizableInstr::insnContext() const {
insnContext = IC_64BIT_VEX_OPSIZE;
else if (OpPrefix == X86Local::PD)
insnContext = IC_VEX_OPSIZE;
else if (HasVEX_LPrefix && OpPrefix == X86Local::XS)
else if (HasVEX_L && OpPrefix == X86Local::XS)
insnContext = IC_VEX_L_XS;
else if (HasVEX_LPrefix && OpPrefix == X86Local::XD)
else if (HasVEX_L && OpPrefix == X86Local::XD)
insnContext = IC_VEX_L_XD;
else if (HasVEX_W && OpPrefix == X86Local::XS)
insnContext = IC_VEX_W_XS;
@ -278,7 +278,7 @@ InstructionContext RecognizableInstr::insnContext() const {
insnContext = IC_VEX_W_XD;
else if (HasVEX_W && OpPrefix == X86Local::PS)
insnContext = IC_VEX_W;
else if (HasVEX_LPrefix && OpPrefix == X86Local::PS)
else if (HasVEX_L && OpPrefix == X86Local::PS)
insnContext = IC_VEX_L;
else if (OpPrefix == X86Local::XD)
insnContext = IC_VEX_XD;

6
llvm/utils/TableGen/X86RecognizableInstr.h
View File

@ -183,12 +183,12 @@ struct RecognizableInstrBase {
bool HasVEX_W;
/// The IgnoresVEX_W field from the record
bool IgnoresVEX_W;
/// Inferred from the operands; indicates whether the L bit in the VEX prefix is set
bool HasVEX_LPrefix;
/// The hasVEX_L field from the record
bool HasVEX_L;
/// The ignoreVEX_L field from the record
bool IgnoresVEX_L;
/// The hasEVEX_L2Prefix field from the record
bool HasEVEX_L2Prefix;
bool HasEVEX_L2;
/// The hasEVEX_K field from the record
bool HasEVEX_K;
/// The hasEVEX_KZ field from the record