forked from OSchip/llvm-project
Moved and expanded convertOpcodeFromRegToImm() to conver more opcodes.
Code beautification for the rest of the code: changed layout to match the rest of the code base. llvm-svn: 6446
This commit is contained in:
Misha Brukman
parent
c1830a472a
commit
a853af587a
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@ -747,8 +747,8 @@ CreateShiftInstructions(const TargetMachine& target,
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//
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Value* shiftDest = destVal;
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unsigned opSize = target.getTargetData().getTypeSize(argVal1->getType());
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if ((shiftOpCode == V9::SLLr6 || shiftOpCode == V9::SLLXr6) && opSize < 8)
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{ // put SLL result into a temporary
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if ((shiftOpCode == V9::SLLr6 || shiftOpCode == V9::SLLXr6) && opSize < 8) {
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// put SLL result into a temporary
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shiftDest = new TmpInstruction(argVal1, optArgVal2, "sllTmp");
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mcfi.addTemp(shiftDest);
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}
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@ -760,8 +760,8 @@ CreateShiftInstructions(const TargetMachine& target,
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.addReg(shiftDest, MOTy::Def);
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mvec.push_back(M);
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if (shiftDest != destVal)
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{ // extend the sign-bit of the result into all upper bits of dest
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if (shiftDest != destVal) {
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// extend the sign-bit of the result into all upper bits of dest
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assert(8*opSize <= 32 && "Unexpected type size > 4 and < IntRegSize?");
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target.getInstrInfo().
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CreateSignExtensionInstructions(target, F, shiftDest, destVal,
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@ -814,16 +814,15 @@ CreateMulConstInstruction(const TargetMachine &target, Function* F,
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else
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M = BuildMI(V9::ADDr,3).addReg(lval).addMReg(Zero).addRegDef(destVal);
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mvec.push_back(M);
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}
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else if (isPowerOf2(C, pow)) {
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} else if (isPowerOf2(C, pow)) {
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unsigned opSize = target.getTargetData().getTypeSize(resultType);
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MachineOpCode opCode = (opSize <= 32)? V9::SLLr6 : V9::SLLXr6;
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CreateShiftInstructions(target, F, opCode, lval, NULL, pow,
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destVal, mvec, mcfi);
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}
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if (mvec.size() > 0 && needNeg)
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{ // insert <reg = SUB 0, reg> after the instr to flip the sign
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if (mvec.size() > 0 && needNeg) {
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// insert <reg = SUB 0, reg> after the instr to flip the sign
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MachineInstr* M = CreateIntNegInstruction(target, destVal);
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mvec.push_back(M);
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}
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@ -862,10 +861,11 @@ CreateCheapestMulConstInstruction(const TargetMachine &target,
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MachineCodeForInstruction& mcfi)
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{
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Value* constOp;
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if (isa<Constant>(lval) && isa<Constant>(rval))
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{ // both operands are constant: evaluate and "set" in dest
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if (isa<Constant>(lval) && isa<Constant>(rval)) {
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// both operands are constant: evaluate and "set" in dest
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Constant* P = ConstantFoldBinaryInstruction(Instruction::Mul,
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cast<Constant>(lval), cast<Constant>(rval));
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cast<Constant>(lval),
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cast<Constant>(rval));
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target.getInstrInfo().CreateCodeToLoadConst(target,F,P,destVal,mvec,mcfi);
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}
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else if (isa<Constant>(rval)) // rval is constant, but not lval
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@ -946,8 +946,7 @@ CreateDivConstInstruction(TargetMachine &target,
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//
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const Type* resultType = instrNode->getInstruction()->getType();
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if (resultType->isInteger())
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{
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if (resultType->isInteger()) {
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unsigned pow;
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bool isValidConst;
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int64_t C = GetConstantValueAsSignedInt(constOp, isValidConst);
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@ -995,8 +994,7 @@ CreateDivConstInstruction(TargetMachine &target,
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// Get the shift operand and "right-shift" opcode to do the divide
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shiftOperand = addTmp;
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opCode = (resultType==Type::LongTy) ? V9::SRAXi6 : V9::SRAi6;
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}
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else {
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} else {
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// Get the shift operand and "right-shift" opcode to do the divide
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shiftOperand = LHS;
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opCode = (resultType==Type::LongTy) ? V9::SRLXi6 : V9::SRLi6;
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@ -1041,8 +1039,7 @@ CreateCodeForVariableSizeAlloca(const TargetMachine& target,
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// Enforce the alignment constraints on the stack pointer at
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// compile time if the total size is a known constant.
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if (isa<Constant>(numElementsVal))
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{
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if (isa<Constant>(numElementsVal)) {
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bool isValid;
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int64_t numElem = GetConstantValueAsSignedInt(numElementsVal, isValid);
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assert(isValid && "Unexpectedly large array dimension in alloca!");
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@ -1050,9 +1047,7 @@ CreateCodeForVariableSizeAlloca(const TargetMachine& target,
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if (int extra= total % target.getFrameInfo().getStackFrameSizeAlignment())
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total += target.getFrameInfo().getStackFrameSizeAlignment() - extra;
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totalSizeVal = ConstantSInt::get(Type::IntTy, total);
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}
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else
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{
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} else {
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// The size is not a constant. Generate code to compute it and
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// code to pad the size for stack alignment.
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// Create a Value to hold the (constant) element size
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@ -1140,39 +1135,6 @@ CreateCodeForFixedSizeAlloca(const TargetMachine& target,
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}
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static unsigned
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convertOpcodeFromRegToImm(unsigned Opcode) {
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switch (Opcode) {
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case V9::ADDr: return V9::ADDi;
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/* load opcodes */
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case V9::LDUBr: return V9::LDUBi;
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case V9::LDSBr: return V9::LDSBi;
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case V9::LDUHr: return V9::LDUHi;
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case V9::LDSHr: return V9::LDSHi;
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case V9::LDUWr: return V9::LDUWi;
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case V9::LDSWr: return V9::LDSWi;
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case V9::LDXr: return V9::LDXi;
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case V9::LDFr: return V9::LDFi;
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case V9::LDDFr: return V9::LDDFi;
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/* store opcodes */
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case V9::STBr: return V9::STBi;
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case V9::STHr: return V9::STHi;
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case V9::STWr: return V9::STWi;
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case V9::STXr: return V9::STXi;
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case V9::STFr: return V9::STFi;
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case V9::STDFr: return V9::STDFi;
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default:
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std::cerr << "Not handled opcode in convert from reg to imm: " << Opcode
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<< "\n";
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abort();
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return 0;
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}
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}
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//------------------------------------------------------------------------
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// Function SetOperandsForMemInstr
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//
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@ -1211,20 +1173,16 @@ SetOperandsForMemInstr(unsigned Opcode,
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// Check if there is an index vector and if so, compute the
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// right offset for structures and for arrays
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//
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if (!idxVec.empty())
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{
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if (!idxVec.empty()) {
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const PointerType* ptrType = cast<PointerType>(ptrVal->getType());
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// If all indices are constant, compute the combined offset directly.
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if (allConstantIndices)
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{
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if (allConstantIndices) {
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// Compute the offset value using the index vector. Create a
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// virtual reg. for it since it may not fit in the immed field.
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uint64_t offset = target.getTargetData().getIndexedOffset(ptrType,idxVec);
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valueForRegOffset = ConstantSInt::get(Type::LongTy, offset);
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}
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else
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{
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} else {
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// There is at least one non-constant offset. Therefore, this must
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// be an array ref, and must have been lowered to a single non-zero
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// offset. (An extra leading zero offset, if any, can be ignored.)
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@ -1264,9 +1222,7 @@ SetOperandsForMemInstr(unsigned Opcode,
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valueForRegOffset = addr;
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}
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}
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else
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{
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} else {
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offsetOpType = MachineOperand::MO_SignExtendedImmed;
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smallConstOffset = 0;
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}
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@ -1279,19 +1235,19 @@ SetOperandsForMemInstr(unsigned Opcode,
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unsigned offsetOpNum, ptrOpNum;
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MachineInstr *MI;
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if (memInst->getOpcode() == Instruction::Store) {
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if (offsetOpType == MachineOperand::MO_VirtualRegister)
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if (offsetOpType == MachineOperand::MO_VirtualRegister) {
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MI = BuildMI(Opcode, 3).addReg(vmInstrNode->leftChild()->getValue())
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.addReg(ptrVal).addReg(valueForRegOffset);
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else {
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} else {
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Opcode = convertOpcodeFromRegToImm(Opcode);
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MI = BuildMI(Opcode, 3).addReg(vmInstrNode->leftChild()->getValue())
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.addReg(ptrVal).addSImm(smallConstOffset);
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}
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} else {
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if (offsetOpType == MachineOperand::MO_VirtualRegister)
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if (offsetOpType == MachineOperand::MO_VirtualRegister) {
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MI = BuildMI(Opcode, 3).addReg(ptrVal).addReg(valueForRegOffset)
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.addRegDef(memInst);
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else {
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} else {
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Opcode = convertOpcodeFromRegToImm(Opcode);
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MI = BuildMI(Opcode, 3).addReg(ptrVal).addSImm(smallConstOffset)
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.addRegDef(memInst);
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@ -1333,33 +1289,31 @@ ForwardOperand(InstructionNode* treeNode,
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// The parent's mvec would be empty if it was itself forwarded.
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// Recursively call ForwardOperand in that case...
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//
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if (mvec.size() == 0)
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{
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if (mvec.size() == 0) {
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assert(parent->parent() != NULL &&
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"Parent could not have been forwarded, yet has no instructions?");
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ForwardOperand(treeNode, parent->parent(), operandNum);
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}
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else
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{
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for (unsigned i=0, N=mvec.size(); i < N; i++)
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{
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} else {
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for (unsigned i=0, N=mvec.size(); i < N; i++) {
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MachineInstr* minstr = mvec[i];
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for (unsigned i=0, numOps=minstr->getNumOperands(); i < numOps; ++i)
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{
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for (unsigned i=0, numOps=minstr->getNumOperands(); i < numOps; ++i) {
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const MachineOperand& mop = minstr->getOperand(i);
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if (mop.getType() == MachineOperand::MO_VirtualRegister &&
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mop.getVRegValue() == unusedOp)
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minstr->SetMachineOperandVal(i,
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MachineOperand::MO_VirtualRegister, fwdOp);
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{
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minstr->SetMachineOperandVal(i, MachineOperand::MO_VirtualRegister,
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fwdOp);
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}
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}
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for (unsigned i=0,numOps=minstr->getNumImplicitRefs(); i<numOps; ++i)
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if (minstr->getImplicitRef(i) == unusedOp)
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if (minstr->getImplicitRef(i) == unusedOp) {
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minstr->setImplicitRef(i, fwdOp,
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minstr->getImplicitOp(i).opIsDefOnly(),
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minstr->getImplicitOp(i).opIsDefAndUse());
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}
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}
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}
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}
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@ -1728,12 +1682,12 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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Instruction* destI = subtreeRoot->getInstruction();
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Value* opVal = subtreeRoot->leftChild()->getValue();
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const Type* opType = opVal->getType();
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if (opType->isIntegral() || isa<PointerType>(opType))
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{
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if (opType->isIntegral() || isa<PointerType>(opType)) {
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unsigned opSize = target.getTargetData().getTypeSize(opType);
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unsigned destSize = target.getTargetData().getTypeSize(destI->getType());
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if (opSize >= destSize)
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{ // Operand is same size as or larger than dest:
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unsigned destSize =
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target.getTargetData().getTypeSize(destI->getType());
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if (opSize >= destSize) {
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// Operand is same size as or larger than dest:
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// zero- or sign-extend, according to the signeddness of
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// the destination (see above).
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if (destI->getType()->isSigned())
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@ -1744,18 +1698,14 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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target.getInstrInfo().CreateZeroExtensionInstructions(target,
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destI->getParent()->getParent(), opVal, destI, 8*destSize,
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mvec, MachineCodeForInstruction::get(destI));
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}
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else
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} else
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forwardOperandNum = 0; // forward first operand to user
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}
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else if (opType->isFloatingPoint())
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{
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} else if (opType->isFloatingPoint()) {
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CreateCodeToConvertFloatToInt(target, opVal, destI, mvec,
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MachineCodeForInstruction::get(destI));
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if (destI->getType()->isUnsigned())
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maskUnsignedResult = true; // not handled by fp->int code
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}
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else
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} else
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assert(0 && "Unrecognized operand type for convert-to-unsigned");
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break;
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@ -1768,13 +1718,11 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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const Type* opType = opVal->getType();
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if (opType->isIntegral() || isa<PointerType>(opType))
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forwardOperandNum = 0; // forward first operand to user
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else if (opType->isFloatingPoint())
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{
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else if (opType->isFloatingPoint()) {
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Instruction* destI = subtreeRoot->getInstruction();
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CreateCodeToConvertFloatToInt(target, opVal, destI, mvec,
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MachineCodeForInstruction::get(destI));
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}
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else
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} else
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assert(0 && "Unrecognized operand type for convert-to-signed");
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break;
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}
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@ -1789,8 +1737,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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// In the future, we'll want to do the same for the FdMULq instruction,
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// so do the check here instead of only for ToFloatTy(reg).
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//
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if (subtreeRoot->parent() != NULL)
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{
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if (subtreeRoot->parent() != NULL) {
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const MachineCodeForInstruction& mcfi =
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MachineCodeForInstruction::get(
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cast<InstructionNode>(subtreeRoot->parent())->getInstruction());
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@ -1798,25 +1745,20 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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forwardOperandNum = 0; // forward first operand to user
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}
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if (forwardOperandNum != 0) // we do need the cast
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{
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if (forwardOperandNum != 0) { // we do need the cast
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Value* leftVal = subtreeRoot->leftChild()->getValue();
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const Type* opType = leftVal->getType();
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MachineOpCode opCode=ChooseConvertToFloatInstr(
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subtreeRoot->getOpLabel(), opType);
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if (opCode == V9::INVALID_OPCODE) // no conversion needed
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{
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if (opCode == V9::INVALID_OPCODE) { // no conversion needed
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forwardOperandNum = 0; // forward first operand to user
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}
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else
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{
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} else {
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// If the source operand is a non-FP type it must be
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// first copied from int to float register via memory!
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Instruction *dest = subtreeRoot->getInstruction();
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Value* srcForCast;
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int n = 0;
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if (! opType->isFloatingPoint())
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{
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if (! opType->isFloatingPoint()) {
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// Create a temporary to represent the FP register
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// into which the integer will be copied via memory.
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// The type of this temporary will determine the FP
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@ -1836,8 +1778,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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dest->getParent()->getParent(),
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leftVal, cast<Instruction>(srcForCast),
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mvec, destMCFI);
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}
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else
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} else
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srcForCast = leftVal;
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M = BuildMI(opCode, 2).addReg(srcForCast).addRegDef(dest);
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@ -1854,8 +1795,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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case 233: // reg: Add(reg, Constant)
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maskUnsignedResult = true;
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M = CreateAddConstInstruction(subtreeRoot);
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if (M != NULL)
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{
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if (M != NULL) {
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mvec.push_back(M);
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break;
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}
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@ -1869,8 +1809,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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case 234: // reg: Sub(reg, Constant)
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maskUnsignedResult = true;
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M = CreateSubConstInstruction(subtreeRoot);
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if (M != NULL)
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{
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if (M != NULL) {
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mvec.push_back(M);
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break;
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}
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@ -2089,8 +2028,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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isFPCompare ? Type::FloatTy : Type::IntTy);
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MachineCodeForInstruction::get(setCCInstr).addTemp(tmpForCC);
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if (! isFPCompare)
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{
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if (! isFPCompare) {
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// Integer condition: dest. should be %g0 or an integer register.
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// If result must be saved but condition is not SetEQ then we need
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// a separate instruction to compute the bool result, so discard
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@ -2111,14 +2049,12 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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}
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mvec.push_back(M);
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if (computeBoolVal)
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{ // recompute bool using the integer condition codes
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if (computeBoolVal) {
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// recompute bool using the integer condition codes
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movOpCode =
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ChooseMovpccAfterSub(subtreeRoot,mustClearReg,valueToMove);
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}
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}
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else
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{
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} else {
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// FP condition: dest of FCMP should be some FCCn register
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M = BuildMI(ChooseFcmpInstruction(subtreeRoot), 3)
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.addCCReg(tmpForCC, MOTy::Def)
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@ -2126,18 +2062,17 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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.addRegDef(subtreeRoot->rightChild()->getValue());
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mvec.push_back(M);
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if (computeBoolVal)
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{// recompute bool using the FP condition codes
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if (computeBoolVal) {
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// recompute bool using the FP condition codes
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mustClearReg = true;
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valueToMove = 1;
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movOpCode = ChooseMovFpccInstruction(subtreeRoot);
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}
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}
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if (computeBoolVal)
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{
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if (mustClearReg)
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{// Unconditionally set register to 0
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if (computeBoolVal) {
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if (mustClearReg) {
|
||||
// Unconditionally set register to 0
|
||||
M = BuildMI(V9::SETHI, 2).addZImm(0).addRegDef(setCCInstr);
|
||||
mvec.push_back(M);
|
||||
}
|
||||
|
|
@ -2192,7 +2127,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
|||
|
||||
if (!isArray ||
|
||||
isa<Constant>(numElementsVal = instr->getArraySize()))
|
||||
{ // total size is constant: generate code for fixed-size alloca
|
||||
{
|
||||
// total size is constant: generate code for fixed-size alloca
|
||||
unsigned numElements = isArray?
|
||||
cast<ConstantUInt>(numElementsVal)->getValue() : 1;
|
||||
CreateCodeForFixedSizeAlloca(target, instr, tsize,
|
||||
|
|
@ -2230,8 +2166,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
|||
// If not, generate the normal call sequence for the function.
|
||||
// This can also handle any intrinsics that are just function calls.
|
||||
//
|
||||
if (! specialIntrinsic)
|
||||
{
|
||||
if (! specialIntrinsic) {
|
||||
// Create hidden virtual register for return address with type void*
|
||||
TmpInstruction* retAddrReg =
|
||||
new TmpInstruction(PointerType::get(Type::VoidTy), callInstr);
|
||||
|
|
@ -2265,16 +2200,14 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
|||
assert(callInstr->getOperand(0) == callee
|
||||
&& "This is assumed in the loop below!");
|
||||
|
||||
for (unsigned i=1, N=callInstr->getNumOperands(); i < N; ++i)
|
||||
{
|
||||
for (unsigned i=1, N=callInstr->getNumOperands(); i < N; ++i) {
|
||||
Value* argVal = callInstr->getOperand(i);
|
||||
Instruction* intArgReg = NULL;
|
||||
|
||||
// Check for FP arguments to varargs functions.
|
||||
// Any such argument in the first $K$ args must be passed in an
|
||||
// integer register, where K = #integer argument registers.
|
||||
if (isVarArgs && argVal->getType()->isFloatingPoint())
|
||||
{
|
||||
if (isVarArgs && argVal->getType()->isFloatingPoint()) {
|
||||
// If it is a function with no prototype, pass value
|
||||
// as an FP value as well as a varargs value
|
||||
if (noPrototype)
|
||||
|
|
@ -2282,8 +2215,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
|||
|
||||
// If this arg. is in the first $K$ regs, add a copy
|
||||
// float-to-int instruction to pass the value as an integer.
|
||||
if (i <= target.getRegInfo().getNumOfIntArgRegs())
|
||||
{
|
||||
if (i <= target.getRegInfo().getNumOfIntArgRegs()) {
|
||||
MachineCodeForInstruction &destMCFI =
|
||||
MachineCodeForInstruction::get(callInstr);
|
||||
intArgReg = new TmpInstruction(Type::IntTy, argVal);
|
||||
|
|
@ -2298,8 +2230,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
|||
|
||||
argDesc->getArgInfo(i-1).setUseIntArgReg();
|
||||
argDesc->getArgInfo(i-1).setArgCopy(intArgReg);
|
||||
}
|
||||
else
|
||||
} else
|
||||
// Cannot fit in first $K$ regs so pass arg on stack
|
||||
argDesc->getArgInfo(i-1).setUseStackSlot();
|
||||
}
|
||||
|
|
@ -2344,7 +2275,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
|||
}
|
||||
|
||||
case 63: // reg: Shr(reg, reg)
|
||||
{ const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
|
||||
{
|
||||
const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
|
||||
assert((opType->isInteger() || isa<PointerType>(opType)) &&
|
||||
"Shr unsupported for other types");
|
||||
Add3OperandInstr(opType->isSigned()
|
||||
|
|
@ -2380,15 +2312,14 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
|||
}
|
||||
}
|
||||
|
||||
if (forwardOperandNum >= 0)
|
||||
{ // We did not generate a machine instruction but need to use operand.
|
||||
if (forwardOperandNum >= 0) {
|
||||
// We did not generate a machine instruction but need to use operand.
|
||||
// If user is in the same tree, replace Value in its machine operand.
|
||||
// If not, insert a copy instruction which should get coalesced away
|
||||
// by register allocation.
|
||||
if (subtreeRoot->parent() != NULL)
|
||||
ForwardOperand(subtreeRoot, subtreeRoot->parent(), forwardOperandNum);
|
||||
else
|
||||
{
|
||||
else {
|
||||
std::vector<MachineInstr*> minstrVec;
|
||||
Instruction* instr = subtreeRoot->getInstruction();
|
||||
target.getInstrInfo().
|
||||
|
|
@ -2402,16 +2333,15 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
|||
}
|
||||
}
|
||||
|
||||
if (maskUnsignedResult)
|
||||
{ // If result is unsigned and smaller than int reg size,
|
||||
if (maskUnsignedResult) {
|
||||
// If result is unsigned and smaller than int reg size,
|
||||
// we need to clear high bits of result value.
|
||||
assert(forwardOperandNum < 0 && "Need mask but no instruction generated");
|
||||
Instruction* dest = subtreeRoot->getInstruction();
|
||||
if (dest->getType()->isUnsigned())
|
||||
{
|
||||
if (dest->getType()->isUnsigned()) {
|
||||
unsigned destSize=target.getTargetData().getTypeSize(dest->getType());
|
||||
if (destSize <= 4)
|
||||
{ // Mask high bits. Use a TmpInstruction to represent the
|
||||
if (destSize <= 4) {
|
||||
// Mask high bits. Use a TmpInstruction to represent the
|
||||
// intermediate result before masking. Since those instructions
|
||||
// have already been generated, go back and substitute tmpI
|
||||
// for dest in the result position of each one of them.
|
||||
|
|
@ -2425,9 +2355,9 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
|||
M = BuildMI(V9::SRLi6, 3).addReg(tmpI).addZImm(8*(4-destSize))
|
||||
.addReg(dest, MOTy::Def);
|
||||
mvec.push_back(M);
|
||||
}
|
||||
else if (destSize < 8)
|
||||
} else if (destSize < 8) {
|
||||
assert(0 && "Unsupported type size: 32 < size < 64 bits");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@
|
|||
#define SPARC_INSTR_SELECTION_SUPPORT_h
|
||||
|
||||
#include "llvm/DerivedTypes.h"
|
||||
#include "SparcInternals.h"
|
||||
|
||||
inline MachineOpCode
|
||||
ChooseLoadInstruction(const Type *DestTy)
|
||||
|
|
@ -77,4 +78,82 @@ ChooseAddInstructionByType(const Type* resultType)
|
|||
return opCode;
|
||||
}
|
||||
|
||||
|
||||
static unsigned
|
||||
convertOpcodeFromRegToImm(unsigned Opcode) {
|
||||
switch (Opcode) {
|
||||
/* arithmetic */
|
||||
case V9::ADDr: return V9::ADDi;
|
||||
case V9::ADDccr: return V9::ADDcci;
|
||||
case V9::ADDCr: return V9::ADDCi;
|
||||
case V9::ADDCccr: return V9::ADDCcci;
|
||||
case V9::SUBr: return V9::SUBi;
|
||||
case V9::SUBccr: return V9::SUBcci;
|
||||
case V9::SUBCr: return V9::SUBCi;
|
||||
case V9::SUBCccr: return V9::SUBCcci;
|
||||
case V9::MULXr: return V9::MULXi;
|
||||
case V9::SDIVXr: return V9::SDIVXi;
|
||||
case V9::UDIVXr: return V9::UDIVXi;
|
||||
|
||||
/* logical */
|
||||
case V9::ANDr: return V9::ANDi;
|
||||
case V9::ANDccr: return V9::ANDcci;
|
||||
case V9::ANDNr: return V9::ANDNi;
|
||||
case V9::ANDNccr: return V9::ANDNcci;
|
||||
case V9::ORr: return V9::ORi;
|
||||
case V9::ORccr: return V9::ORcci;
|
||||
case V9::ORNr: return V9::ORNi;
|
||||
case V9::ORNccr: return V9::ORNcci;
|
||||
case V9::XORr: return V9::XORi;
|
||||
case V9::XORccr: return V9::XORcci;
|
||||
case V9::XNORr: return V9::XNORi;
|
||||
case V9::XNORccr: return V9::XNORcci;
|
||||
|
||||
/* shift */
|
||||
case V9::SLLr6: return V9::SLLi6;
|
||||
case V9::SRLr6: return V9::SRLi6;
|
||||
case V9::SRAr6: return V9::SRAi6;
|
||||
case V9::SLLXr6: return V9::SLLXi6;
|
||||
case V9::SRLXr6: return V9::SRLXi6;
|
||||
case V9::SRAXr6: return V9::SRAXi6;
|
||||
|
||||
/* load */
|
||||
case V9::LDSBr: return V9::LDSBi;
|
||||
case V9::LDSHr: return V9::LDSHi;
|
||||
case V9::LDSWr: return V9::LDSWi;
|
||||
case V9::LDUBr: return V9::LDUBi;
|
||||
case V9::LDUHr: return V9::LDUHi;
|
||||
case V9::LDUWr: return V9::LDUWi;
|
||||
case V9::LDXr: return V9::LDXi;
|
||||
case V9::LDFr: return V9::LDFi;
|
||||
case V9::LDDFr: return V9::LDDFi;
|
||||
case V9::LDQFr: return V9::LDQFi;
|
||||
case V9::LDFSRr: return V9::LDFSRi;
|
||||
case V9::LDXFSRr: return V9::LDXFSRi;
|
||||
|
||||
/* store */
|
||||
case V9::STBr: return V9::STBi;
|
||||
case V9::STHr: return V9::STHi;
|
||||
case V9::STWr: return V9::STWi;
|
||||
case V9::STXr: return V9::STXi;
|
||||
case V9::STFr: return V9::STFi;
|
||||
case V9::STDFr: return V9::STDFi;
|
||||
case V9::STFSRr: return V9::STFSRi;
|
||||
case V9::STXFSRr: return V9::STXFSRi;
|
||||
|
||||
/* jump & return */
|
||||
case V9::JMPLCALLr: return V9::JMPLCALLi;
|
||||
case V9::JMPLRETr: return V9::JMPLRETi;
|
||||
case V9::RETURNr: return V9::RETURNi;
|
||||
|
||||
/* save and restore */
|
||||
case V9::SAVEr: return V9::SAVEi;
|
||||
case V9::RESTOREr: return V9::RESTOREi;
|
||||
|
||||
default:
|
||||
// It's already in correct format
|
||||
return Opcode;
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue