forked from OSchip/llvm-project
[AArch64] Regenerate some more tests
This updates the check lines in some extra tests, to make them more maintainable going forward.
This commit is contained in:
David Green
parent
0776924a17
commit
a84b78198c
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@ -1,33 +1,40 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
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; Transform "a == C ? C : x" to "a == C ? a : x" to avoid materializing C.
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; CHECK-LABEL: test1:
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; CHECK: cmp w[[REG1:[0-9]+]], #2
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; CHECK: mov w[[REG2:[0-9]+]], #7
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; CHECK: csel w0, w[[REG1]], w[[REG2]], eq
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define i32 @test1(i32 %x) {
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; CHECK-LABEL: test1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp w0, #2
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; CHECK-NEXT: mov w8, #7
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; CHECK-NEXT: csel w0, w0, w8, eq
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; CHECK-NEXT: ret
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%cmp = icmp eq i32 %x, 2
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%res = select i1 %cmp, i32 2, i32 7
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ret i32 %res
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}
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; Transform "a == C ? C : x" to "a == C ? a : x" to avoid materializing C.
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; CHECK-LABEL: test2:
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; CHECK: cmp x[[REG1:[0-9]+]], #2
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; CHECK: mov w[[REG2:[0-9]+]], #7
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; CHECK: csel x0, x[[REG1]], x[[REG2]], eq
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define i64 @test2(i64 %x) {
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; CHECK-LABEL: test2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x0, #2
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; CHECK-NEXT: mov w8, #7
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; CHECK-NEXT: csel x0, x0, x8, eq
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; CHECK-NEXT: ret
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%cmp = icmp eq i64 %x, 2
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%res = select i1 %cmp, i64 2, i64 7
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ret i64 %res
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}
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; Transform "a != C ? x : C" to "a != C ? x : a" to avoid materializing C.
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; CHECK-LABEL: test3:
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; CHECK: cmp x[[REG1:[0-9]+]], #7
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; CHECK: mov w[[REG2:[0-9]+]], #2
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; CHECK: csel x0, x[[REG2]], x[[REG1]], ne
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define i64 @test3(i64 %x) {
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; CHECK-LABEL: test3:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x0, #7
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; CHECK-NEXT: mov w8, #2
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; CHECK-NEXT: csel x0, x8, x0, ne
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; CHECK-NEXT: ret
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%cmp = icmp ne i64 %x, 7
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%res = select i1 %cmp, i64 2, i64 7
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ret i64 %res
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@ -35,11 +42,13 @@ define i64 @test3(i64 %x) {
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; Don't transform "a == C ? C : x" to "a == C ? a : x" if a == 0. If we did we
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; would needlessly extend the live range of x0 when we can just use xzr.
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; CHECK-LABEL: test4:
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; CHECK: cmp x0, #0
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; CHECK: mov w8, #7
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; CHECK: csel x0, xzr, x8, eq
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define i64 @test4(i64 %x) {
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; CHECK-LABEL: test4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x0, #0
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; CHECK-NEXT: mov w8, #7
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; CHECK-NEXT: csel x0, xzr, x8, eq
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; CHECK-NEXT: ret
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%cmp = icmp eq i64 %x, 0
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%res = select i1 %cmp, i64 0, i64 7
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ret i64 %res
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@ -48,11 +57,13 @@ define i64 @test4(i64 %x) {
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; Don't transform "a == C ? C : x" to "a == C ? a : x" if a == 1. If we did we
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; would needlessly extend the live range of x0 when we can just use xzr with
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; CSINC to materialize the 1.
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; CHECK-LABEL: test5:
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; CHECK: cmp x0, #1
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; CHECK: mov w[[REG:[0-9]+]], #7
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; CHECK: csinc x0, x[[REG]], xzr, ne
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define i64 @test5(i64 %x) {
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; CHECK-LABEL: test5:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x0, #1
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; CHECK-NEXT: mov w8, #7
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; CHECK-NEXT: csinc x0, x8, xzr, ne
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; CHECK-NEXT: ret
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%cmp = icmp eq i64 %x, 1
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%res = select i1 %cmp, i64 1, i64 7
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ret i64 %res
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@ -61,38 +72,46 @@ define i64 @test5(i64 %x) {
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; Don't transform "a == C ? C : x" to "a == C ? a : x" if a == -1. If we did we
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; would needlessly extend the live range of x0 when we can just use xzr with
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; CSINV to materialize the -1.
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; CHECK-LABEL: test6:
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; CHECK: cmn x0, #1
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; CHECK: mov w[[REG:[0-9]+]], #7
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; CHECK: csinv x0, x[[REG]], xzr, ne
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define i64 @test6(i64 %x) {
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; CHECK-LABEL: test6:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmn x0, #1
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; CHECK-NEXT: mov w8, #7
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; CHECK-NEXT: csinv x0, x8, xzr, ne
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; CHECK-NEXT: ret
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%cmp = icmp eq i64 %x, -1
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%res = select i1 %cmp, i64 -1, i64 7
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ret i64 %res
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}
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; CHECK-LABEL: test7:
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; CHECK: cmp x[[REG:[0-9]]], #7
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; CHECK: csinc x0, x[[REG]], xzr, eq
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define i64 @test7(i64 %x) {
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; CHECK-LABEL: test7:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x0, #7
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; CHECK-NEXT: csinc x0, x0, xzr, eq
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; CHECK-NEXT: ret
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%cmp = icmp eq i64 %x, 7
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%res = select i1 %cmp, i64 7, i64 1
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ret i64 %res
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}
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; CHECK-LABEL: test8:
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; CHECK: cmp x[[REG:[0-9]]], #7
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; CHECK: csinc x0, x[[REG]], xzr, eq
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define i64 @test8(i64 %x) {
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; CHECK-LABEL: test8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x0, #7
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; CHECK-NEXT: csinc x0, x0, xzr, eq
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; CHECK-NEXT: ret
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%cmp = icmp ne i64 %x, 7
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%res = select i1 %cmp, i64 1, i64 7
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ret i64 %res
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}
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; CHECK-LABEL: test9:
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; CHECK: cmp x[[REG:[0-9]]], #7
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; CHECK: csinv x0, x[[REG]], xzr, eq
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define i64 @test9(i64 %x) {
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; CHECK-LABEL: test9:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x0, #7
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; CHECK-NEXT: csinv x0, x0, xzr, eq
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; CHECK-NEXT: ret
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%cmp = icmp eq i64 %x, 7
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%res = select i1 %cmp, i64 7, i64 -1
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ret i64 %res
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@ -100,10 +119,12 @@ define i64 @test9(i64 %x) {
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; Rather than use a CNEG, use a CSINV to transform "a == 1 ? 1 : -1" to
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; "a == 1 ? a : -1" to avoid materializing a constant.
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; CHECK-LABEL: test10:
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; CHECK: cmp w[[REG:[0-9]]], #1
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; CHECK: csinv w0, w[[REG]], wzr, eq
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define i32 @test10(i32 %x) {
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; CHECK-LABEL: test10:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp w0, #1
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; CHECK-NEXT: csinv w0, w0, wzr, eq
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; CHECK-NEXT: ret
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%cmp = icmp eq i32 %x, 1
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%res = select i1 %cmp, i32 1, i32 -1
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ret i32 %res
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@ -1,3 +1,4 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon,+fullfp16 < %s -o -| FileCheck %s
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declare half @llvm.fabs.f16(half)
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@ -8,11 +9,13 @@ declare fp128 @llvm.fabs.f128(fp128)
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; INFINITY requires loading the constant for _Float16
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define i32 @replace_isinf_call_f16(half %x) {
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; CHECK-LABEL: replace_isinf_call_f16:
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; CHECK: adrp [[ADDR:x[0-9]+]], [[CSTLABEL:.LCP.*]]
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; CHECK: ldr [[INFINITY:h[0-9]+]], {{[[]}}[[ADDR]], :lo12:[[CSTLABEL]]{{[]]}}
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; CHECK-NEXT: fabs [[ABS:h[0-9]+]], h0
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; CHECK-NEXT: fcmp [[ABS]], [[INFINITY]]
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; CHECK-NEXT: cset w0, eq
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI0_0
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; CHECK-NEXT: ldr h1, [x8, :lo12:.LCPI0_0]
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; CHECK-NEXT: fabs h0, h0
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; CHECK-NEXT: fcmp h0, h1
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%abs = tail call half @llvm.fabs.f16(half %x)
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%cmpinf = fcmp oeq half %abs, 0xH7C00
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%ret = zext i1 %cmpinf to i32
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@ -22,11 +25,13 @@ define i32 @replace_isinf_call_f16(half %x) {
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; Check if INFINITY for float is materialized
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define i32 @replace_isinf_call_f32(float %x) {
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; CHECK-LABEL: replace_isinf_call_f32:
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; CHECK: mov [[INFSCALARREG:w[0-9]+]], #2139095040
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; CHECK-NEXT: fabs [[ABS:s[0-9]+]], s0
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; CHECK-NEXT: fmov [[INFREG:s[0-9]+]], [[INFSCALARREG]]
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; CHECK-NEXT: fcmp [[ABS]], [[INFREG]]
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; CHECK-NEXT: cset w0, eq
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #2139095040
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; CHECK-NEXT: fabs s0, s0
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; CHECK-NEXT: fmov s1, w8
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; CHECK-NEXT: fcmp s0, s1
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%abs = tail call float @llvm.fabs.f32(float %x)
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%cmpinf = fcmp oeq float %abs, 0x7FF0000000000000
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%ret = zext i1 %cmpinf to i32
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@ -36,11 +41,13 @@ define i32 @replace_isinf_call_f32(float %x) {
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; Check if INFINITY for double is materialized
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define i32 @replace_isinf_call_f64(double %x) {
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; CHECK-LABEL: replace_isinf_call_f64:
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; CHECK: mov [[INFSCALARREG:x[0-9]+]], #9218868437227405312
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; CHECK-NEXT: fabs [[ABS:d[0-9]+]], d0
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; CHECK-NEXT: fmov [[INFREG:d[0-9]+]], [[INFSCALARREG]]
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; CHECK-NEXT: fcmp [[ABS]], [[INFREG]]
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; CHECK-NEXT: cset w0, eq
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, #9218868437227405312
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; CHECK-NEXT: fabs d0, d0
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; CHECK-NEXT: fmov d1, x8
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; CHECK-NEXT: fcmp d0, d1
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%abs = tail call double @llvm.fabs.f64(double %x)
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%cmpinf = fcmp oeq double %abs, 0x7FF0000000000000
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%ret = zext i1 %cmpinf to i32
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@ -50,11 +57,24 @@ define i32 @replace_isinf_call_f64(double %x) {
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; For long double it still requires loading the constant.
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define i32 @replace_isinf_call_f128(fp128 %x) {
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; CHECK-LABEL: replace_isinf_call_f128:
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; CHECK: adrp [[ADDR:x[0-9]+]], [[CSTLABEL:.LCP.*]]
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; CHECK: ldr q1, {{[[]}}[[ADDR]], :lo12:[[CSTLABEL]]{{[]]}}
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; CHECK: bl __eqtf2
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; CHECK: cmp w0, #0
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; CHECK: cset w0, eq
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #32
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; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: .cfi_offset w30, -16
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; CHECK-NEXT: str q0, [sp]
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; CHECK-NEXT: ldrb w8, [sp, #15]
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; CHECK-NEXT: and w8, w8, #0x7f
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; CHECK-NEXT: strb w8, [sp, #15]
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; CHECK-NEXT: adrp x8, .LCPI3_0
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; CHECK-NEXT: ldr q0, [sp]
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; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI3_0]
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; CHECK-NEXT: bl __eqtf2
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; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
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; CHECK-NEXT: cmp w0, #0
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: add sp, sp, #32
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; CHECK-NEXT: ret
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%abs = tail call fp128 @llvm.fabs.f128(fp128 %x)
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%cmpinf = fcmp oeq fp128 %abs, 0xL00000000000000007FFF000000000000
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%ret = zext i1 %cmpinf to i32
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@ -1,19 +1,21 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-apple-ios -fast-isel -verify-machineinstrs | FileCheck %s
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; Check that the kill flag is cleared between CSE'd instructions on their
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; imp-def'd registers.
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; The verifier would complain otherwise.
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define i64 @csed-impdef-killflag(i64 %a) {
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; CHECK-LABEL: csed-impdef-killflag
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; CHECK-DAG: mov [[REG1:w[0-9]+]], #1
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; CHECK-DAG: mov [[REG2:x[0-9]+]], #2
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; CHECK-DAG: mov [[REG3:x[0-9]+]], #3
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; CHECK-DAG: cmp x0, #0
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; CHECK: csel w[[SELECT_WREG_1:[0-9]+]], wzr, [[REG1]], ne
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; CHECK-DAG: csel [[SELECT_XREG_2:x[0-9]+]], [[REG2]], [[REG3]], ne
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; CHECK: ubfx [[SELECT_XREG_1:x[0-9]+]], x[[SELECT_WREG_1]], #0, #32
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; CHECK-NEXT: add x0, [[SELECT_XREG_2]], [[SELECT_XREG_1]]
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; CHECK-NEXT: ret
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define i64 @csed_impdef_killflag(i64 %a) {
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; CHECK-LABEL: csed_impdef_killflag:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: mov w8, #1
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; CHECK-NEXT: cmp x0, #0
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; CHECK-NEXT: mov x9, #2
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; CHECK-NEXT: mov x10, #3
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; CHECK-NEXT: csel w8, wzr, w8, ne
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; CHECK-NEXT: csel x9, x9, x10, ne
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; CHECK-NEXT: ubfx x8, x8, #0, #32
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; CHECK-NEXT: add x0, x9, x8
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; CHECK-NEXT: ret
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%1 = icmp ne i64 %a, 0
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%2 = select i1 %1, i32 0, i32 1
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@ -1,18 +1,24 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=arm64-apple-ios7.0 %s -o - | FileCheck %s
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; RUN: llc -mtriple=aarch64_be-linux-gnu %s -o - | FileCheck --check-prefix=CHECK-BE %s
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define i128 @test_128bitmul(i128 %lhs, i128 %rhs) {
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; CHECK-LABEL: test_128bitmul:
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; CHECK-DAG: umulh [[CARRY:x[0-9]+]], x0, x2
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; CHECK-DAG: madd [[PART1:x[0-9]+]], x0, x3, [[CARRY]]
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; CHECK: madd x1, x1, x2, [[PART1]]
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; CHECK: mul x0, x0, x2
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; CHECK: ; %bb.0:
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; CHECK-NEXT: umulh x8, x0, x2
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; CHECK-NEXT: madd x8, x0, x3, x8
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; CHECK-NEXT: madd x1, x1, x2, x8
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; CHECK-NEXT: mul x0, x0, x2
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; CHECK-NEXT: ret
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;
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; CHECK-BE-LABEL: test_128bitmul:
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; CHECK-BE-DAG: umulh [[CARRY:x[0-9]+]], x1, x3
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; CHECK-BE-DAG: madd [[PART1:x[0-9]+]], x1, x2, [[CARRY]]
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; CHECK-BE: madd x0, x0, x3, [[PART1]]
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; CHECK-BE: mul x1, x1, x3
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; CHECK-BE: // %bb.0:
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; CHECK-BE-NEXT: umulh x8, x1, x3
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; CHECK-BE-NEXT: madd x8, x1, x2, x8
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; CHECK-BE-NEXT: madd x0, x0, x3, x8
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; CHECK-BE-NEXT: mul x1, x1, x3
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; CHECK-BE-NEXT: ret
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%prod = mul i128 %lhs, %rhs
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ret i128 %prod
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@ -1,3 +1,4 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -o - %s | FileCheck %s
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; RUN: llc -mtriple=aarch64-linux-gnu -stop-after=finalize-isel -o - %s | FileCheck --check-prefix=MIR %s
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@ -12,12 +13,13 @@
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; MIR-NEXT: STRQui killed %2, %0, 0 :: (store (s128) into %ir.p0, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]])
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define i32 @test_memcpy(i32* nocapture %p, i32* nocapture readonly %q) {
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; CHECK-LABEL: test_memcpy:
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; CHECK-DAG: ldp [[Q0:w[0-9]+]], [[Q1:w[0-9]+]], [x1]
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; CHECK-DAG: ldr [[PVAL:q[0-9]+]], [x0, #16]
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; CHECK-DAG: add w8, [[Q0]], [[Q1]]
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; CHECK: str [[PVAL]], [x0]
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; CHECK: mov w0, w8
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; CHECK: ret
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp w8, w9, [x1]
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; CHECK-NEXT: ldr q0, [x0, #16]
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; CHECK-NEXT: add w8, w8, w9
|
||||
; CHECK-NEXT: str q0, [x0]
|
||||
; CHECK-NEXT: mov w0, w8
|
||||
; CHECK-NEXT: ret
|
||||
%p0 = bitcast i32* %p to i8*
|
||||
%add.ptr = getelementptr inbounds i32, i32* %p, i64 4
|
||||
%p1 = bitcast i32* %add.ptr to i8*
|
||||
|
|
@ -34,12 +36,13 @@ define i32 @test_memcpy(i32* nocapture %p, i32* nocapture readonly %q) {
|
|||
; MIR-NEXT: STRQui killed %2, %0, 0 :: (store (s128) into %ir.p0, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]])
|
||||
define i32 @test_memcpy_inline(i32* nocapture %p, i32* nocapture readonly %q) {
|
||||
; CHECK-LABEL: test_memcpy_inline:
|
||||
; CHECK-DAG: ldp [[Q0:w[0-9]+]], [[Q1:w[0-9]+]], [x1]
|
||||
; CHECK-DAG: ldr [[PVAL:q[0-9]+]], [x0, #16]
|
||||
; CHECK-DAG: add w8, [[Q0]], [[Q1]]
|
||||
; CHECK: str [[PVAL]], [x0]
|
||||
; CHECK: mov w0, w8
|
||||
; CHECK: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldp w8, w9, [x1]
|
||||
; CHECK-NEXT: ldr q0, [x0, #16]
|
||||
; CHECK-NEXT: add w8, w8, w9
|
||||
; CHECK-NEXT: str q0, [x0]
|
||||
; CHECK-NEXT: mov w0, w8
|
||||
; CHECK-NEXT: ret
|
||||
%p0 = bitcast i32* %p to i8*
|
||||
%add.ptr = getelementptr inbounds i32, i32* %p, i64 4
|
||||
%p1 = bitcast i32* %add.ptr to i8*
|
||||
|
|
@ -56,12 +59,13 @@ define i32 @test_memcpy_inline(i32* nocapture %p, i32* nocapture readonly %q) {
|
|||
; MIR-NEXT: STRQui killed %2, %0, 0 :: (store (s128) into %ir.p0, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]])
|
||||
define i32 @test_memmove(i32* nocapture %p, i32* nocapture readonly %q) {
|
||||
; CHECK-LABEL: test_memmove:
|
||||
; CHECK-DAG: ldp [[Q0:w[0-9]+]], [[Q1:w[0-9]+]], [x1]
|
||||
; CHECK-DAG: ldr [[PVAL:q[0-9]+]], [x0, #16]
|
||||
; CHECK-DAG: add w8, [[Q0]], [[Q1]]
|
||||
; CHECK: str [[PVAL]], [x0]
|
||||
; CHECK: mov w0, w8
|
||||
; CHECK: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldp w8, w9, [x1]
|
||||
; CHECK-NEXT: ldr q0, [x0, #16]
|
||||
; CHECK-NEXT: add w8, w8, w9
|
||||
; CHECK-NEXT: str q0, [x0]
|
||||
; CHECK-NEXT: mov w0, w8
|
||||
; CHECK-NEXT: ret
|
||||
%p0 = bitcast i32* %p to i8*
|
||||
%add.ptr = getelementptr inbounds i32, i32* %p, i64 4
|
||||
%p1 = bitcast i32* %add.ptr to i8*
|
||||
|
|
@ -79,12 +83,13 @@ define i32 @test_memmove(i32* nocapture %p, i32* nocapture readonly %q) {
|
|||
; MIR-NEXT: STRXui %2, %0, 0 :: (store (s64) into %ir.p0, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]])
|
||||
define i32 @test_memset(i32* nocapture %p, i32* nocapture readonly %q) {
|
||||
; CHECK-LABEL: test_memset:
|
||||
; CHECK-DAG: ldp [[Q0:w[0-9]+]], [[Q1:w[0-9]+]], [x1]
|
||||
; CHECK-DAG: mov [[PVAL:x[0-9]+]], #-6148914691236517206
|
||||
; CHECK: stp [[PVAL]], [[PVAL]], [x0]
|
||||
; CHECK: add w8, [[Q0]], [[Q1]]
|
||||
; CHECK: mov w0, w8
|
||||
; CHECK: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldp w8, w9, [x1]
|
||||
; CHECK-NEXT: mov x10, #-6148914691236517206
|
||||
; CHECK-NEXT: stp x10, x10, [x0]
|
||||
; CHECK-NEXT: add w8, w8, w9
|
||||
; CHECK-NEXT: mov w0, w8
|
||||
; CHECK-NEXT: ret
|
||||
%p0 = bitcast i32* %p to i8*
|
||||
tail call void @llvm.memset.p0i8.i64(i8* noundef nonnull align 4 dereferenceable(16) %p0, i8 170, i64 16, i1 false), !alias.scope !2, !noalias !4
|
||||
%v0 = load i32, i32* %q, align 4, !alias.scope !4, !noalias !2
|
||||
|
|
@ -99,12 +104,13 @@ define i32 @test_memset(i32* nocapture %p, i32* nocapture readonly %q) {
|
|||
; MIR-NEXT: STRQui killed %2, %0, 0 :: (store (s128) into %ir.p0, align 1, !alias.scope ![[SET0]], !noalias ![[SET1]])
|
||||
define i32 @test_mempcpy(i32* nocapture %p, i32* nocapture readonly %q) {
|
||||
; CHECK-LABEL: test_mempcpy:
|
||||
; CHECK-DAG: ldp [[Q0:w[0-9]+]], [[Q1:w[0-9]+]], [x1]
|
||||
; CHECK-DAG: ldr [[PVAL:q[0-9]+]], [x0, #16]
|
||||
; CHECK-DAG: add w8, [[Q0]], [[Q1]]
|
||||
; CHECK: str [[PVAL]], [x0]
|
||||
; CHECK: mov w0, w8
|
||||
; CHECK: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldp w8, w9, [x1]
|
||||
; CHECK-NEXT: ldr q0, [x0, #16]
|
||||
; CHECK-NEXT: add w8, w8, w9
|
||||
; CHECK-NEXT: str q0, [x0]
|
||||
; CHECK-NEXT: mov w0, w8
|
||||
; CHECK-NEXT: ret
|
||||
%p0 = bitcast i32* %p to i8*
|
||||
%add.ptr = getelementptr inbounds i32, i32* %p, i64 4
|
||||
%p1 = bitcast i32* %add.ptr to i8*
|
||||
|
|
|
|||
|
|
@ -1,51 +1,68 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 | FileCheck %s
|
||||
|
||||
define i64 @test0() {
|
||||
; CHECK-LABEL: test0:
|
||||
; CHECK: ; %bb.0:
|
||||
; CHECK-NEXT: mov x0, xzr
|
||||
; CHECK-NEXT: ret
|
||||
; Not produced by move wide instructions, but good to make sure we can return 0 anyway:
|
||||
; CHECK: mov x0, xzr
|
||||
ret i64 0
|
||||
}
|
||||
|
||||
define i64 @test1() {
|
||||
; CHECK-LABEL: test1:
|
||||
; CHECK: mov w0, #1
|
||||
; CHECK: ; %bb.0:
|
||||
; CHECK-NEXT: mov w0, #1
|
||||
; CHECK-NEXT: ret
|
||||
ret i64 1
|
||||
}
|
||||
|
||||
define i64 @test2() {
|
||||
; CHECK-LABEL: test2:
|
||||
; CHECK: mov w0, #65535
|
||||
; CHECK: ; %bb.0:
|
||||
; CHECK-NEXT: mov w0, #65535
|
||||
; CHECK-NEXT: ret
|
||||
ret i64 65535
|
||||
}
|
||||
|
||||
define i64 @test3() {
|
||||
; CHECK-LABEL: test3:
|
||||
; CHECK: mov w0, #65536
|
||||
; CHECK: ; %bb.0:
|
||||
; CHECK-NEXT: mov w0, #65536
|
||||
; CHECK-NEXT: ret
|
||||
ret i64 65536
|
||||
}
|
||||
|
||||
define i64 @test4() {
|
||||
; CHECK-LABEL: test4:
|
||||
; CHECK: mov w0, #-65536
|
||||
; CHECK: ; %bb.0:
|
||||
; CHECK-NEXT: mov w0, #-65536
|
||||
; CHECK-NEXT: ret
|
||||
ret i64 4294901760
|
||||
}
|
||||
|
||||
define i64 @test5() {
|
||||
; CHECK-LABEL: test5:
|
||||
; CHECK: mov x0, #4294967296
|
||||
; CHECK: ; %bb.0:
|
||||
; CHECK-NEXT: mov x0, #4294967296
|
||||
; CHECK-NEXT: ret
|
||||
ret i64 4294967296
|
||||
}
|
||||
|
||||
define i64 @test6() {
|
||||
; CHECK-LABEL: test6:
|
||||
; CHECK: mov x0, #281470681743360
|
||||
; CHECK: ; %bb.0:
|
||||
; CHECK-NEXT: mov x0, #281470681743360
|
||||
; CHECK-NEXT: ret
|
||||
ret i64 281470681743360
|
||||
}
|
||||
|
||||
define i64 @test7() {
|
||||
; CHECK-LABEL: test7:
|
||||
; CHECK: mov x0, #281474976710656
|
||||
; CHECK: ; %bb.0:
|
||||
; CHECK-NEXT: mov x0, #281474976710656
|
||||
; CHECK-NEXT: ret
|
||||
ret i64 281474976710656
|
||||
}
|
||||
|
||||
|
|
@ -53,19 +70,25 @@ define i64 @test7() {
|
|||
; couldn't. Useful even for i64
|
||||
define i64 @test8() {
|
||||
; CHECK-LABEL: test8:
|
||||
; CHECK: mov w0, #-60876
|
||||
; CHECK: ; %bb.0:
|
||||
; CHECK-NEXT: mov w0, #-60876
|
||||
; CHECK-NEXT: ret
|
||||
ret i64 4294906420
|
||||
}
|
||||
|
||||
define i64 @test9() {
|
||||
; CHECK-LABEL: test9:
|
||||
; CHECK: mov x0, #-1
|
||||
; CHECK: ; %bb.0:
|
||||
; CHECK-NEXT: mov x0, #-1
|
||||
; CHECK-NEXT: ret
|
||||
ret i64 -1
|
||||
}
|
||||
|
||||
define i64 @test10() {
|
||||
; CHECK-LABEL: test10:
|
||||
; CHECK: mov x0, #-3989504001
|
||||
; CHECK: ; %bb.0:
|
||||
; CHECK-NEXT: mov x0, #-3989504001
|
||||
; CHECK-NEXT: ret
|
||||
ret i64 18446744069720047615
|
||||
}
|
||||
|
||||
|
|
@ -75,50 +98,75 @@ define i64 @test10() {
|
|||
|
||||
define void @test11() {
|
||||
; CHECK-LABEL: test11:
|
||||
; CHECK: str wzr
|
||||
; CHECK: ; %bb.0:
|
||||
; CHECK-NEXT: adrp x8, _var32@PAGE
|
||||
; CHECK-NEXT: str wzr, [x8, _var32@PAGEOFF]
|
||||
; CHECK-NEXT: ret
|
||||
store i32 0, i32* @var32
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test12() {
|
||||
; CHECK-LABEL: test12:
|
||||
; CHECK: mov {{w[0-9]+}}, #1
|
||||
; CHECK: ; %bb.0:
|
||||
; CHECK-NEXT: adrp x8, _var32@PAGE
|
||||
; CHECK-NEXT: mov w9, #1
|
||||
; CHECK-NEXT: str w9, [x8, _var32@PAGEOFF]
|
||||
; CHECK-NEXT: ret
|
||||
store i32 1, i32* @var32
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test13() {
|
||||
; CHECK-LABEL: test13:
|
||||
; CHECK: mov {{w[0-9]+}}, #65535
|
||||
; CHECK: ; %bb.0:
|
||||
; CHECK-NEXT: adrp x8, _var32@PAGE
|
||||
; CHECK-NEXT: mov w9, #65535
|
||||
; CHECK-NEXT: str w9, [x8, _var32@PAGEOFF]
|
||||
; CHECK-NEXT: ret
|
||||
store i32 65535, i32* @var32
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test14() {
|
||||
; CHECK-LABEL: test14:
|
||||
; CHECK: mov {{w[0-9]+}}, #65536
|
||||
; CHECK: ; %bb.0:
|
||||
; CHECK-NEXT: adrp x8, _var32@PAGE
|
||||
; CHECK-NEXT: mov w9, #65536
|
||||
; CHECK-NEXT: str w9, [x8, _var32@PAGEOFF]
|
||||
; CHECK-NEXT: ret
|
||||
store i32 65536, i32* @var32
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test15() {
|
||||
; CHECK-LABEL: test15:
|
||||
; CHECK: mov {{w[0-9]+}}, #-65536
|
||||
; CHECK: ; %bb.0:
|
||||
; CHECK-NEXT: adrp x8, _var32@PAGE
|
||||
; CHECK-NEXT: mov w9, #-65536
|
||||
; CHECK-NEXT: str w9, [x8, _var32@PAGEOFF]
|
||||
; CHECK-NEXT: ret
|
||||
store i32 4294901760, i32* @var32
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test16() {
|
||||
; CHECK-LABEL: test16:
|
||||
; CHECK: mov {{w[0-9]+}}, #-1
|
||||
; CHECK: ; %bb.0:
|
||||
; CHECK-NEXT: adrp x8, _var32@PAGE
|
||||
; CHECK-NEXT: mov w9, #-1
|
||||
; CHECK-NEXT: str w9, [x8, _var32@PAGEOFF]
|
||||
; CHECK-NEXT: ret
|
||||
store i32 -1, i32* @var32
|
||||
ret void
|
||||
}
|
||||
|
||||
define i64 @test17() {
|
||||
; CHECK-LABEL: test17:
|
||||
; CHECK: ; %bb.0:
|
||||
; CHECK-NEXT: mov x0, #-3
|
||||
; CHECK-NEXT: ret
|
||||
|
||||
; Mustn't MOVN w0 here.
|
||||
; CHECK: mov x0, #-3
|
||||
ret i64 -3
|
||||
}
|
||||
|
|
|
|||
|
|
@ -268,7 +268,7 @@ define <vscale x 4 x i32> @sub_i32_ptrue_all_d(<vscale x 4 x i32> %a) #0 {
|
|||
define <vscale x 16 x i8> @subr_i8(<vscale x 16 x i8> %a) {
|
||||
; CHECK-LABEL: subr_i8:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: subr z0.b, z0.b, #127
|
||||
; CHECK-NEXT: subr z0.b, z0.b, #127 // =0x7f
|
||||
; CHECK-NEXT: ret
|
||||
%pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
|
||||
%elt = insertelement <vscale x 16 x i8> undef, i8 127, i32 0
|
||||
|
|
@ -282,7 +282,7 @@ define <vscale x 16 x i8> @subr_i8(<vscale x 16 x i8> %a) {
|
|||
define <vscale x 8 x i16> @subr_i16(<vscale x 8 x i16> %a) {
|
||||
; CHECK-LABEL: subr_i16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: subr z0.h, z0.h, #127
|
||||
; CHECK-NEXT: subr z0.h, z0.h, #127 // =0x7f
|
||||
; CHECK-NEXT: ret
|
||||
%pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
|
||||
%elt = insertelement <vscale x 8 x i16> undef, i16 127, i32 0
|
||||
|
|
@ -312,7 +312,7 @@ define <vscale x 8 x i16> @subr_i16_out_of_range(<vscale x 8 x i16> %a) {
|
|||
define <vscale x 4 x i32> @subr_i32(<vscale x 4 x i32> %a) {
|
||||
; CHECK-LABEL: subr_i32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: subr z0.s, z0.s, #127
|
||||
; CHECK-NEXT: subr z0.s, z0.s, #127 // =0x7f
|
||||
; CHECK-NEXT: ret
|
||||
%pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
|
||||
%elt = insertelement <vscale x 4 x i32> undef, i32 127, i32 0
|
||||
|
|
@ -342,7 +342,7 @@ define <vscale x 4 x i32> @subr_i32_out_of_range(<vscale x 4 x i32> %a) {
|
|||
define <vscale x 2 x i64> @subr_i64(<vscale x 2 x i64> %a) {
|
||||
; CHECK-LABEL: subr_i64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: subr z0.d, z0.d, #127
|
||||
; CHECK-NEXT: subr z0.d, z0.d, #127 // =0x7f
|
||||
; CHECK-NEXT: ret
|
||||
%pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
|
||||
%elt = insertelement <vscale x 2 x i64> undef, i64 127, i64 0
|
||||
|
|
@ -372,8 +372,9 @@ define <vscale x 2 x i64> @subr_i64_out_of_range(<vscale x 2 x i64> %a) {
|
|||
; As subr_i32 but where pg is i8 based and thus compatible for i32.
|
||||
define <vscale x 4 x i32> @subr_i32_ptrue_all_b(<vscale x 4 x i32> %a) #0 {
|
||||
; CHECK-LABEL: subr_i32_ptrue_all_b:
|
||||
; CHECK: subr z0.s, z0.s, #1
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: subr z0.s, z0.s, #1 // =0x1
|
||||
; CHECK-NEXT: ret
|
||||
%pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
|
||||
%pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)
|
||||
%b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1)
|
||||
|
|
@ -386,8 +387,9 @@ define <vscale x 4 x i32> @subr_i32_ptrue_all_b(<vscale x 4 x i32> %a) #0 {
|
|||
; As subr_i32 but where pg is i16 based and thus compatible for i32.
|
||||
define <vscale x 4 x i32> @subr_i32_ptrue_all_h(<vscale x 4 x i32> %a) #0 {
|
||||
; CHECK-LABEL: subr_i32_ptrue_all_h:
|
||||
; CHECK: subr z0.s, z0.s, #1
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: subr z0.s, z0.s, #1 // =0x1
|
||||
; CHECK-NEXT: ret
|
||||
%pg.h = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
|
||||
%pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %pg.h)
|
||||
%pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)
|
||||
|
|
@ -402,10 +404,11 @@ define <vscale x 4 x i32> @subr_i32_ptrue_all_h(<vscale x 4 x i32> %a) #0 {
|
|||
; thus inactive lanes are important and the immediate form cannot be used.
|
||||
define <vscale x 4 x i32> @subr_i32_ptrue_all_d(<vscale x 4 x i32> %a) #0 {
|
||||
; CHECK-LABEL: subr_i32_ptrue_all_d:
|
||||
; CHECK-DAG: ptrue [[PG:p[0-9]+]].d
|
||||
; CHECK-DAG: mov [[DUP:z[0-9]+]].s, #1
|
||||
; CHECK-DAG: subr z0.s, [[PG]]/m, z0.s, [[DUP]].s
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ptrue p0.d
|
||||
; CHECK-NEXT: mov z1.s, #1 // =0x1
|
||||
; CHECK-NEXT: subr z0.s, p0/m, z0.s, z1.s
|
||||
; CHECK-NEXT: ret
|
||||
%pg.d = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
|
||||
%pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %pg.d)
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%pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)
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Reference in New Issue