forked from OSchip/llvm-project
parent
b4e1687270
commit
a81e1cab04
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@ -216,7 +216,8 @@ public:
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/// getRegClassVirtRegs - Return the list of virtual registers of the given
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/// getRegClassVirtRegs - Return the list of virtual registers of the given
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/// target register class.
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/// target register class.
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std::vector<unsigned> &getRegClassVirtRegs(const TargetRegisterClass *RC) {
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const std::vector<unsigned> &
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getRegClassVirtRegs(const TargetRegisterClass *RC) const {
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return RegClass2VRegMap[RC->getID()];
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return RegClass2VRegMap[RC->getID()];
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}
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}
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@ -1154,7 +1154,7 @@ PreAllocSplitting::SplitRegLiveIntervals(const TargetRegisterClass **RCs,
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// codegen is not modelling. Ignore these barriers for now.
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// codegen is not modelling. Ignore these barriers for now.
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if (!TII->isSafeToMoveRegClassDefs(*RC))
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if (!TII->isSafeToMoveRegClassDefs(*RC))
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continue;
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continue;
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std::vector<unsigned> &VRs = MRI->getRegClassVirtRegs(*RC);
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const std::vector<unsigned> &VRs = MRI->getRegClassVirtRegs(*RC);
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for (unsigned i = 0, e = VRs.size(); i != e; ++i) {
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for (unsigned i = 0, e = VRs.size(); i != e; ++i) {
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unsigned Reg = VRs[i];
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unsigned Reg = VRs[i];
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if (!LIs->hasInterval(Reg))
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if (!LIs->hasInterval(Reg))
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