forked from OSchip/llvm-project
Revert "[AMDGPU] Invert the handling of skip insertion."
This reverts commit 0dc6c249bf.
The commit is reported to cause a regression in piglit/bin/glsl-vs-loop for
Mesa.
This commit is contained in:
Nicolai Hähnle
parent
e15fb06e2d
commit
a80291ce10
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@ -156,9 +156,6 @@ extern char &SIWholeQuadModeID;
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void initializeSILowerControlFlowPass(PassRegistry &);
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extern char &SILowerControlFlowID;
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void initializeSIRemoveShortExecBranchesPass(PassRegistry &);
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extern char &SIRemoveShortExecBranchesID;
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void initializeSIInsertSkipsPass(PassRegistry &);
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extern char &SIInsertSkipsPassID;
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@ -228,7 +228,6 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
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initializeSIModeRegisterPass(*PR);
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initializeSIWholeQuadModePass(*PR);
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initializeSILowerControlFlowPass(*PR);
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initializeSIRemoveShortExecBranchesPass(*PR);
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initializeSIInsertSkipsPass(*PR);
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initializeSIMemoryLegalizerPass(*PR);
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initializeSIOptimizeExecMaskingPass(*PR);
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@ -994,7 +993,6 @@ void GCNPassConfig::addPreEmitPass() {
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// be better for it to emit S_NOP <N> when possible.
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addPass(&PostRAHazardRecognizerID);
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addPass(&SIRemoveShortExecBranchesID);
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addPass(&SIInsertSkipsPassID);
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addPass(&BranchRelaxationPassID);
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}
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@ -116,7 +116,6 @@ add_llvm_target(AMDGPUCodeGen
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SIOptimizeExecMaskingPreRA.cpp
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SIPeepholeSDWA.cpp
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SIRegisterInfo.cpp
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SIRemoveShortExecBranches.cpp
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SIShrinkInstructions.cpp
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SIWholeQuadMode.cpp
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GCNILPSched.cpp
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@ -41,7 +41,7 @@ using namespace llvm;
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#define DEBUG_TYPE "si-insert-skips"
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static cl::opt<unsigned> SkipThresholdFlag(
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"amdgpu-skip-threshold-legacy",
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"amdgpu-skip-threshold",
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cl::desc("Number of instructions before jumping over divergent control flow"),
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cl::init(12), cl::Hidden);
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@ -466,9 +466,6 @@ bool SIInsertSkips::runOnMachineFunction(MachineFunction &MF) {
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MachineInstr &MI = *I;
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switch (MI.getOpcode()) {
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case AMDGPU::S_CBRANCH_EXECZ:
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ExecBranchStack.push_back(MI.getOperand(0).getMBB());
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break;
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case AMDGPU::SI_MASK_BRANCH:
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ExecBranchStack.push_back(MI.getOperand(0).getMBB());
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MadeChange |= skipMaskBranch(MI, MBB);
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@ -244,9 +244,9 @@ void SILowerControlFlow::emitIf(MachineInstr &MI) {
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BuildMI(MBB, I, DL, TII->get(MovTermOpc), Exec)
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.addReg(Tmp, RegState::Kill);
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// Insert the S_CBRANCH_EXECZ instruction which will be optimized later
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// during SIRemoveShortExecBranches.
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MachineInstr *NewBr = BuildMI(MBB, I, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
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// Insert a pseudo terminator to help keep the verifier happy. This will also
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// be used later when inserting skips.
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MachineInstr *NewBr = BuildMI(MBB, I, DL, TII->get(AMDGPU::SI_MASK_BRANCH))
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.add(MI.getOperand(2));
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if (!LIS) {
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@ -323,8 +323,8 @@ void SILowerControlFlow::emitElse(MachineInstr &MI) {
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.addReg(DstReg);
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MachineInstr *Branch =
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BuildMI(MBB, ElsePt, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
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.addMBB(DestBB);
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BuildMI(MBB, ElsePt, DL, TII->get(AMDGPU::SI_MASK_BRANCH))
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.addMBB(DestBB);
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if (!LIS) {
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MI.eraseFromParent();
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@ -1,158 +0,0 @@
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//===-- SIRemoveShortExecBranches.cpp ------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This pass optmizes the s_cbranch_execz instructions.
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/// The pass removes this skip instruction for short branches,
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/// if there is no unwanted sideeffect in the fallthrough code sequence.
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///
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPUSubtarget.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "SIInstrInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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#define DEBUG_TYPE "si-remove-short-exec-branches"
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static unsigned SkipThreshold;
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static cl::opt<unsigned, true> SkipThresholdFlag(
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"amdgpu-skip-threshold", cl::Hidden,
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cl::desc(
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"Number of instructions before jumping over divergent control flow"),
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cl::location(SkipThreshold), cl::init(12));
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namespace {
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class SIRemoveShortExecBranches : public MachineFunctionPass {
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private:
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const SIInstrInfo *TII = nullptr;
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bool getBlockDestinations(MachineBasicBlock &SrcMBB,
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MachineBasicBlock *&TrueMBB,
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MachineBasicBlock *&FalseMBB,
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SmallVectorImpl<MachineOperand> &Cond);
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bool mustRetainExeczBranch(const MachineBasicBlock &From,
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const MachineBasicBlock &To) const;
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bool removeExeczBranch(MachineInstr &MI, MachineBasicBlock &SrcMBB);
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public:
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static char ID;
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SIRemoveShortExecBranches() : MachineFunctionPass(ID) {
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initializeSIRemoveShortExecBranchesPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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};
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} // End anonymous namespace.
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INITIALIZE_PASS(SIRemoveShortExecBranches, DEBUG_TYPE,
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"SI remove short exec branches", false, false)
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char SIRemoveShortExecBranches::ID = 0;
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char &llvm::SIRemoveShortExecBranchesID = SIRemoveShortExecBranches::ID;
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bool SIRemoveShortExecBranches::getBlockDestinations(
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MachineBasicBlock &SrcMBB, MachineBasicBlock *&TrueMBB,
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MachineBasicBlock *&FalseMBB, SmallVectorImpl<MachineOperand> &Cond) {
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if (TII->analyzeBranch(SrcMBB, TrueMBB, FalseMBB, Cond))
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return false;
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if (!FalseMBB)
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FalseMBB = SrcMBB.getNextNode();
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return true;
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}
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bool SIRemoveShortExecBranches::mustRetainExeczBranch(
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const MachineBasicBlock &From, const MachineBasicBlock &To) const {
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unsigned NumInstr = 0;
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const MachineFunction *MF = From.getParent();
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for (MachineFunction::const_iterator MBBI(&From), ToI(&To), End = MF->end();
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MBBI != End && MBBI != ToI; ++MBBI) {
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const MachineBasicBlock &MBB = *MBBI;
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for (MachineBasicBlock::const_iterator I = MBB.begin(), E = MBB.end();
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I != E; ++I) {
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// When a uniform loop is inside non-uniform control flow, the branch
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// leaving the loop might be an S_CBRANCH_VCCNZ, which is never taken
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// when EXEC = 0. We should skip the loop lest it becomes infinite.
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if (I->getOpcode() == AMDGPU::S_CBRANCH_VCCNZ ||
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I->getOpcode() == AMDGPU::S_CBRANCH_VCCZ)
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return true;
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if (TII->hasUnwantedEffectsWhenEXECEmpty(*I))
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return true;
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// These instructions are potentially expensive even if EXEC = 0.
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if (TII->isSMRD(*I) || TII->isVMEM(*I) || TII->isFLAT(*I) ||
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I->getOpcode() == AMDGPU::S_WAITCNT)
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return true;
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++NumInstr;
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if (NumInstr >= SkipThreshold)
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return true;
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}
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}
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return false;
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}
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// Returns true if the skip branch instruction is removed.
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bool SIRemoveShortExecBranches::removeExeczBranch(MachineInstr &MI,
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MachineBasicBlock &SrcMBB) {
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MachineBasicBlock *TrueMBB = nullptr;
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MachineBasicBlock *FalseMBB = nullptr;
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SmallVector<MachineOperand, 1> Cond;
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if (!getBlockDestinations(SrcMBB, TrueMBB, FalseMBB, Cond))
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return false;
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// Consider only the forward branches.
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if ((SrcMBB.getNumber() >= TrueMBB->getNumber()) ||
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mustRetainExeczBranch(*FalseMBB, *TrueMBB))
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return false;
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LLVM_DEBUG(dbgs() << "Removing the execz branch: " << MI);
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MI.eraseFromParent();
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SrcMBB.removeSuccessor(TrueMBB);
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return true;
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}
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bool SIRemoveShortExecBranches::runOnMachineFunction(MachineFunction &MF) {
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const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
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TII = ST.getInstrInfo();
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MF.RenumberBlocks();
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bool Changed = false;
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for (MachineBasicBlock &MBB : MF) {
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MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
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if (MBBI == MBB.end())
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continue;
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MachineInstr &MI = *MBBI;
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switch (MI.getOpcode()) {
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case AMDGPU::S_CBRANCH_EXECZ:
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Changed = removeExeczBranch(MI, MBB);
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break;
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default:
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break;
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}
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}
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return Changed;
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}
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@ -10,8 +10,9 @@ define i32 @divergent_if_swap_brtarget_order0(i32 %value) {
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; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
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; CHECK-NEXT: ; implicit-def: $vgpr0
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; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
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; CHECK-NEXT: ; mask branch BB0_2
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; CHECK-NEXT: s_cbranch_execz BB0_2
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; CHECK-NEXT: ; %bb.1: ; %if.true
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; CHECK-NEXT: BB0_1: ; %if.true
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; CHECK-NEXT: global_load_dword v0, v[0:1], off
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; CHECK-NEXT: BB0_2: ; %endif
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; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
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@ -37,10 +38,12 @@ define i32 @divergent_if_swap_brtarget_order1(i32 %value) {
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; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
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; CHECK-NEXT: ; implicit-def: $vgpr0
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; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
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; CHECK-NEXT: s_cbranch_execnz BB1_2
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; CHECK-NEXT: ; %bb.1: ; %if.true
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; CHECK-NEXT: ; mask branch BB1_2
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; CHECK-NEXT: BB1_1: ; %endif
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; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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; CHECK-NEXT: BB1_2: ; %if.true
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; CHECK-NEXT: global_load_dword v0, v[0:1], off
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; CHECK-NEXT: BB1_2: ; %endif
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; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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File diff suppressed because it is too large
Load Diff
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@ -11,7 +11,7 @@ declare void @llvm.amdgcn.raw.buffer.store.f32(float, <4 x i32>, i32, i32, i32 i
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; Show that what the atomic optimization pass will do for raw buffers.
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; GCN-LABEL: add_i32_constant:
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; %bb.{{[0-9]+}}:
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; GCN-LABEL: BB0_1:
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; GCN32: v_cmp_ne_u32_e64 s[[exec_lo:[0-9]+]], 1, 0
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; GCN64: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0
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; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0
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@ -14,11 +14,12 @@
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; GCN-DAG: v_cmp_lt_f32_e32 vcc,
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; GCN: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[OTHERCC]]
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; GCN: s_and_saveexec_b64 [[SAVED:s\[[0-9]+:[0-9]+\]]], [[AND]]
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; GCN: ; mask branch [[BB5:BB[0-9]+_[0-9]+]]
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; GCN-NEXT: ; %bb.{{[0-9]+}}: ; %bb4
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; GCN-NEXT: BB{{[0-9]+_[0-9]+}}: ; %bb4
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; GCN: ds_write_b32
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; GCN: ; %bb.{{[0-9]+}}:
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; GCN: [[BB5]]
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; GCN-NEXT: s_endpgm
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; GCN-NEXT: .Lfunc_end
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define amdgpu_ps void @ham(float %arg, float %arg1) #0 {
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@ -389,6 +389,7 @@ bb3:
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; GCN-LABEL: {{^}}uniform_inside_divergent:
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; GCN: v_cmp_gt_u32_e32 vcc, 16, v{{[0-9]+}}
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; GCN-NEXT: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc
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; GCN-NEXT: ; mask branch [[ENDIF:BB[0-9]+_[0-9]+]]
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; GCN-NEXT: s_cbranch_execnz [[IF:BB[0-9]+_[0-9]+]]
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; GCN-NEXT: [[LONGBB:BB[0-9]+_[0-9]+]]: ; %entry
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@ -400,7 +401,7 @@ bb3:
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; GCN-NEXT: [[IF]]: ; %if
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; GCN: buffer_store_dword
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; GCN: s_cmp_lg_u32
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; GCN: s_cbranch_scc1 [[ENDIF:BB[0-9]+_[0-9]+]]
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; GCN: s_cbranch_scc1 [[ENDIF]]
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; GCN-NEXT: ; %bb.2: ; %if_uniform
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; GCN: buffer_store_dword
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@ -437,10 +438,12 @@ endif:
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; GCN: v_cmp_nlt_f32_e32 vcc
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; GCN-NEXT: s_and_saveexec_b64 [[TEMP_MASK:s\[[0-9]+:[0-9]+\]]], vcc
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; GCN-NEXT: s_xor_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], exec, [[TEMP_MASK]]
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; GCN-NEXT: ; mask branch [[FLOW:BB[0-9]+_[0-9]+]]
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; GCN: BB{{[0-9]+_[0-9]+}}: ; %Flow
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; GCN: [[FLOW]]: ; %Flow
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; GCN-NEXT: s_or_saveexec_b64 [[TEMP_MASK1:s\[[0-9]+:[0-9]+\]]], [[MASK]]
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; GCN-NEXT: s_xor_b64 exec, exec, [[TEMP_MASK1]]
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; GCN-NEXT: ; mask branch [[RET:BB[0-9]+_[0-9]+]]
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; GCN: [[LOOP_BODY:BB[0-9]+_[0-9]+]]: ; %loop{{$}}
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; GCN: ;;#ASMSTART
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@ -451,7 +454,7 @@ endif:
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; GCN: v_nop_e64
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; GCN: v_nop_e64
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; GCN: ;;#ASMEND
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; GCN: s_cbranch_vccz [[RET:BB[0-9]+_[0-9]+]]
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; GCN: s_cbranch_vccz [[RET]]
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; GCN-NEXT: [[LONGBB:BB[0-9]+_[0-9]+]]: ; %loop
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; GCN-NEXT: ; in Loop: Header=[[LOOP_BODY]] Depth=1
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@ -8,7 +8,8 @@ define hidden void @func() #1 {
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; GCN-LABEL: {{^}}if_call:
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; GCN: s_and_saveexec_b64
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; GCN-NEXT: s_cbranch_execz [[END:BB[0-9]+_[0-9]+]]
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; GCN-NEXT: ; mask branch [[END:BB[0-9]+_[0-9]+]]
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; GCN-NEXT: s_cbranch_execz [[END]]
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; GCN: s_swappc_b64
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; GCN: [[END]]:
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define void @if_call(i32 %flag) #0 {
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@ -25,7 +26,8 @@ end:
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; GCN-LABEL: {{^}}if_asm:
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; GCN: s_and_saveexec_b64
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; GCN-NEXT: s_cbranch_execz [[END:BB[0-9]+_[0-9]+]]
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; GCN-NEXT: ; mask branch [[END:BB[0-9]+_[0-9]+]]
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; GCN-NEXT: s_cbranch_execz [[END]]
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; GCN: ; sample asm
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; GCN: [[END]]:
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define void @if_asm(i32 %flag) #0 {
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@ -42,7 +44,8 @@ end:
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; GCN-LABEL: {{^}}if_call_kernel:
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; GCN: s_and_saveexec_b64
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; GCN-NEXT: s_cbranch_execz BB3_2
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; GCN-NEXT: ; mask branch [[END:BB[0-9]+_[0-9]+]]
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; GCN-NEXT: s_cbranch_execz [[END]]
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; GCN: s_swappc_b64
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define amdgpu_kernel void @if_call_kernel() #0 {
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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|
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@ -3,10 +3,12 @@
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; ALL-LABEL: {{^}}simple_nested_if:
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; GCN: s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9:]+\]]]
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; GCN-NEXT: s_cbranch_execz [[ENDIF:BB[0-9_]+]]
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; GCN: s_and_b64 exec, exec, vcc
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; GCN-NEXT: ; mask branch [[ENDIF:BB[0-9_]+]]
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; GCN-NEXT: s_cbranch_execz [[ENDIF]]
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; GCN-NEXT: ; %bb.{{[0-9]+}}:
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; GCN: s_and_b64 exec, exec, vcc
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; GCN-NEXT: ; mask branch [[ENDIF]]
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; GCN-NEXT: s_cbranch_execz [[ENDIF]]
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; GCN-NEXT: {{^BB[0-9_]+}}:
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; GCN: store_dword
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; GCN-NEXT: {{^}}[[ENDIF]]:
|
||||
; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC]]
|
||||
|
|
@ -41,10 +43,12 @@ bb.outer.end: ; preds = %bb.outer.then, %bb.
|
|||
|
||||
; ALL-LABEL: {{^}}uncollapsable_nested_if:
|
||||
; GCN: s_and_saveexec_b64 [[SAVEEXEC_OUTER:s\[[0-9:]+\]]]
|
||||
; GCN-NEXT: s_cbranch_execz [[ENDIF_OUTER:BB[0-9_]+]]
|
||||
; GCN-NEXT: ; mask branch [[ENDIF_OUTER:BB[0-9_]+]]
|
||||
; GCN-NEXT: s_cbranch_execz [[ENDIF_OUTER]]
|
||||
; GCN: s_and_saveexec_b64 [[SAVEEXEC_INNER:s\[[0-9:]+\]]]
|
||||
; GCN-NEXT: s_cbranch_execz [[ENDIF_INNER:BB[0-9_]+]]
|
||||
; GCN-NEXT: ; %bb.{{[0-9]+}}:
|
||||
; GCN-NEXT: ; mask branch [[ENDIF_INNER:BB[0-9_]+]]
|
||||
; GCN-NEXT: s_cbranch_execz [[ENDIF_INNER]]
|
||||
; GCN-NEXT: {{^BB[0-9_]+}}:
|
||||
; GCN: store_dword
|
||||
; GCN-NEXT: {{^}}[[ENDIF_INNER]]:
|
||||
; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_INNER]]
|
||||
|
|
@ -84,16 +88,18 @@ bb.outer.end: ; preds = %bb.inner.then, %bb
|
|||
|
||||
; ALL-LABEL: {{^}}nested_if_if_else:
|
||||
; GCN: s_and_saveexec_b64 [[SAVEEXEC_OUTER:s\[[0-9:]+\]]]
|
||||
; GCN-NEXT: s_cbranch_execz [[ENDIF_OUTER:BB[0-9_]+]]
|
||||
; GCN-NEXT: ; mask branch [[ENDIF_OUTER:BB[0-9_]+]]
|
||||
; GCN-NEXT: s_cbranch_execz [[ENDIF_OUTER]]
|
||||
; GCN: s_and_saveexec_b64 [[SAVEEXEC_INNER:s\[[0-9:]+\]]]
|
||||
; GCN-NEXT: s_xor_b64 [[SAVEEXEC_INNER2:s\[[0-9:]+\]]], exec, [[SAVEEXEC_INNER]]
|
||||
; GCN-NEXT: s_cbranch_execz [[THEN_INNER:BB[0-9_]+]]
|
||||
; GCN-NEXT: ; %bb.{{[0-9]+}}:
|
||||
; GCN-NEXT: ; mask branch [[THEN_INNER:BB[0-9_]+]]
|
||||
; GCN-NEXT: s_cbranch_execz [[THEN_INNER]]
|
||||
; GCN-NEXT: {{^BB[0-9_]+}}:
|
||||
; GCN: store_dword
|
||||
; GCN-NEXT: {{^}}[[THEN_INNER]]:
|
||||
; GCN-NEXT: s_or_saveexec_b64 [[SAVEEXEC_INNER3:s\[[0-9:]+\]]], [[SAVEEXEC_INNER2]]
|
||||
; GCN-NEXT: s_xor_b64 exec, exec, [[SAVEEXEC_INNER3]]
|
||||
; GCN-NEXT: s_cbranch_execz [[ENDIF_OUTER]]
|
||||
; GCN-NEXT: ; mask branch [[ENDIF_OUTER]]
|
||||
; GCN: store_dword
|
||||
; GCN-NEXT: {{^}}[[ENDIF_OUTER]]:
|
||||
; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_OUTER]]
|
||||
|
|
@ -131,24 +137,28 @@ bb.outer.end: ; preds = %bb, %bb.then, %b
|
|||
; ALL-LABEL: {{^}}nested_if_else_if:
|
||||
; GCN: s_and_saveexec_b64 [[SAVEEXEC_OUTER:s\[[0-9:]+\]]]
|
||||
; GCN-NEXT: s_xor_b64 [[SAVEEXEC_OUTER2:s\[[0-9:]+\]]], exec, [[SAVEEXEC_OUTER]]
|
||||
; GCN-NEXT: s_cbranch_execz [[THEN_OUTER:BB[0-9_]+]]
|
||||
; GCN-NEXT: ; %bb.{{[0-9]+}}:
|
||||
; GCN-NEXT: ; mask branch [[THEN_OUTER:BB[0-9_]+]]
|
||||
; GCN-NEXT: s_cbranch_execz [[THEN_OUTER]]
|
||||
; GCN-NEXT: {{^BB[0-9_]+}}:
|
||||
; GCN: store_dword
|
||||
; GCN-NEXT: s_and_saveexec_b64 [[SAVEEXEC_INNER_IF_OUTER_ELSE:s\[[0-9:]+\]]]
|
||||
; GCN-NEXT: s_cbranch_execz [[THEN_OUTER_FLOW:BB[0-9_]+]]
|
||||
; GCN-NEXT: ; %bb.{{[0-9]+}}:
|
||||
; GCN-NEXT: ; mask branch [[THEN_OUTER_FLOW:BB[0-9_]+]]
|
||||
; GCN-NEXT: s_cbranch_execz [[THEN_OUTER_FLOW]]
|
||||
; GCN-NEXT: {{^BB[0-9_]+}}:
|
||||
; GCN: store_dword
|
||||
; GCN-NEXT: {{^}}[[THEN_OUTER_FLOW]]:
|
||||
; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_INNER_IF_OUTER_ELSE]]
|
||||
; GCN-NEXT: {{^}}[[THEN_OUTER]]:
|
||||
; GCN-NEXT: s_or_saveexec_b64 [[SAVEEXEC_OUTER3:s\[[0-9:]+\]]], [[SAVEEXEC_OUTER2]]
|
||||
; GCN-NEXT: s_xor_b64 exec, exec, [[SAVEEXEC_OUTER3]]
|
||||
; GCN-NEXT: s_cbranch_execz [[ENDIF_OUTER:BB[0-9_]+]]
|
||||
; GCN-NEXT: ; %bb.{{[0-9]+}}:
|
||||
; GCN-NEXT: ; mask branch [[ENDIF_OUTER:BB[0-9_]+]]
|
||||
; GCN-NEXT: s_cbranch_execz [[ENDIF_OUTER]]
|
||||
; GCN-NEXT: {{^BB[0-9_]+}}:
|
||||
; GCN: store_dword
|
||||
; GCN-NEXT: s_and_saveexec_b64 [[SAVEEXEC_INNER_IF_OUTER_THEN:s\[[0-9:]+\]]]
|
||||
; GCN-NEXT: s_cbranch_execz [[FLOW1:BB[0-9_]+]]
|
||||
; GCN-NEXT: ; %bb.{{[0-9]+}}:
|
||||
; GCN-NEXT: ; mask branch [[FLOW1:BB[0-9_]+]]
|
||||
; GCN-NEXT: s_cbranch_execz [[FLOW1]]
|
||||
; GCN-NEXT: {{^BB[0-9_]+}}:
|
||||
; GCN: store_dword
|
||||
; GCN-NEXT: [[FLOW1]]:
|
||||
; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_INNER_IF_OUTER_THEN]]
|
||||
|
|
@ -193,8 +203,9 @@ bb.outer.end:
|
|||
|
||||
; ALL-LABEL: {{^}}s_endpgm_unsafe_barrier:
|
||||
; GCN: s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9:]+\]]]
|
||||
; GCN-NEXT: s_cbranch_execz [[ENDIF:BB[0-9_]+]]
|
||||
; GCN-NEXT: ; %bb.{{[0-9]+}}:
|
||||
; GCN-NEXT: ; mask branch [[ENDIF:BB[0-9_]+]]
|
||||
; GCN-NEXT: s_cbranch_execz [[ENDIF]]
|
||||
; GCN-NEXT: {{^BB[0-9_]+}}:
|
||||
; GCN: store_dword
|
||||
; GCN-NEXT: {{^}}[[ENDIF]]:
|
||||
; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC]]
|
||||
|
|
|
|||
|
|
@ -35,9 +35,9 @@
|
|||
|
||||
; GCN: s_mov_b64 exec, s{{\[}}[[ANDEXEC_LO]]:[[ANDEXEC_HI]]{{\]}}
|
||||
|
||||
; GCN: s_cbranch_execz [[ENDIF:BB[0-9]+_[0-9]+]]
|
||||
; GCN: mask branch [[ENDIF:BB[0-9]+_[0-9]+]]
|
||||
|
||||
; GCN: ; %bb.{{[0-9]+}}: ; %if
|
||||
; GCN: {{^}}BB{{[0-9]+}}_1: ; %if
|
||||
; GCN: s_mov_b32 m0, -1
|
||||
; GCN: ds_read_b32 [[LOAD1:v[0-9]+]]
|
||||
; GCN: buffer_load_dword [[RELOAD_LOAD0:v[0-9]+]], off, s[0:3], s7 offset:[[LOAD0_OFFSET]] ; 4-byte Folded Reload
|
||||
|
|
@ -116,7 +116,8 @@ endif:
|
|||
|
||||
; GCN: s_mov_b64 exec, s{{\[}}[[ANDEXEC_LO]]:[[ANDEXEC_HI]]{{\]}}
|
||||
|
||||
; GCN-NEXT: s_cbranch_execz [[END:BB[0-9]+_[0-9]+]]
|
||||
; GCN-NEXT: ; mask branch [[END:BB[0-9]+_[0-9]+]]
|
||||
; GCN-NEXT: s_cbranch_execz [[END]]
|
||||
|
||||
|
||||
; GCN: [[LOOP:BB[0-9]+_[0-9]+]]:
|
||||
|
|
@ -193,7 +194,8 @@ end:
|
|||
; GCN: s_mov_b64 exec, [[CMP0]]
|
||||
|
||||
; FIXME: It makes no sense to put this skip here
|
||||
; GCN: s_cbranch_execz [[FLOW:BB[0-9]+_[0-9]+]]
|
||||
; GCN-NEXT: ; mask branch [[FLOW:BB[0-9]+_[0-9]+]]
|
||||
; GCN: s_cbranch_execz [[FLOW]]
|
||||
; GCN-NEXT: s_branch [[ELSE:BB[0-9]+_[0-9]+]]
|
||||
|
||||
; GCN: [[FLOW]]: ; %Flow
|
||||
|
|
@ -227,10 +229,11 @@ end:
|
|||
|
||||
; GCN: buffer_store_dword [[FLOW_VAL]], off, s[0:3], s7 offset:[[RESULT_OFFSET:[0-9]+]] ; 4-byte Folded Spill
|
||||
; GCN: s_xor_b64 exec, exec, s{{\[}}[[FLOW_S_RELOAD_SAVEEXEC_LO]]:[[FLOW_S_RELOAD_SAVEEXEC_HI]]{{\]}}
|
||||
; GCN-NEXT: s_cbranch_execz [[ENDIF:BB[0-9]+_[0-9]+]]
|
||||
; GCN-NEXT: ; mask branch [[ENDIF:BB[0-9]+_[0-9]+]]
|
||||
; GCN-NEXT: s_cbranch_execz [[ENDIF]]
|
||||
|
||||
|
||||
; GCN: ; %bb.{{[0-9]+}}: ; %if
|
||||
; GCN: BB{{[0-9]+}}_2: ; %if
|
||||
; GCN: ds_read_b32
|
||||
; GCN: buffer_load_dword v[[LOAD0_RELOAD:[0-9]+]], off, s[0:3], s7 offset:[[LOAD0_OFFSET]] ; 4-byte Folded Reload
|
||||
; GCN: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, v{{[0-9]+}}, v[[LOAD0_RELOAD]]
|
||||
|
|
|
|||
|
|
@ -4,8 +4,8 @@ declare i32 @llvm.amdgcn.workitem.id.x() #0
|
|||
; GCN-LABEL: {{^}}convergent_inlineasm:
|
||||
; GCN: %bb.0:
|
||||
; GCN: v_cmp_ne_u32_e64
|
||||
; GCN: s_cbranch_execz
|
||||
; GCN: ; %bb.{{[0-9]+}}:
|
||||
; GCN: ; mask branch
|
||||
; GCN: BB{{[0-9]+_[0-9]+}}:
|
||||
define amdgpu_kernel void @convergent_inlineasm(i64 addrspace(1)* nocapture %arg) {
|
||||
bb:
|
||||
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
|
|
@ -23,9 +23,9 @@ bb5: ; preds = %bb3, %bb
|
|||
}
|
||||
|
||||
; GCN-LABEL: {{^}}nonconvergent_inlineasm:
|
||||
; GCN: s_cbranch_execz
|
||||
; GCN: ; mask branch
|
||||
|
||||
; GCN: ; %bb.{{[0-9]+}}:
|
||||
; GCN: BB{{[0-9]+_[0-9]+}}:
|
||||
; GCN: v_cmp_ne_u32_e64
|
||||
|
||||
; GCN: BB{{[0-9]+_[0-9]+}}:
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
; CHECK: s_mov_b32 [[SREG:s[0-9]+]], 1.0
|
||||
; CHECK: %bb.1:
|
||||
; CHECK-NOT: v_mov_b32_e32 {{v[0-9]+}}, 1.0
|
||||
; CHECK: BB0_3:
|
||||
; CHECK: BB0_4:
|
||||
; CHECK: v_mov_b32_e32 v{{[0-9]+}}, [[SREG]]
|
||||
|
||||
define amdgpu_ps void @mov_opt(i32 %arg, i32 inreg %arg1, i32 inreg %arg2) local_unnamed_addr #0 {
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@ define amdgpu_ps void @main(i32, float) {
|
|||
; CHECK-NEXT: s_and_b64 s[8:9], s[8:9], exec
|
||||
; CHECK-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
|
||||
; CHECK-NEXT: s_andn2_b64 exec, exec, s[2:3]
|
||||
; CHECK-NEXT: s_cbranch_execz BB0_6
|
||||
; CHECK-NEXT: BB0_3: ; %loop
|
||||
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
|
||||
; CHECK-NEXT: s_or_b64 s[6:7], s[6:7], exec
|
||||
|
|
@ -43,19 +44,21 @@ define amdgpu_ps void @main(i32, float) {
|
|||
; CHECK-NEXT: s_mov_b64 s[6:7], -1
|
||||
; CHECK-NEXT: s_and_saveexec_b64 s[8:9], vcc
|
||||
; CHECK-NEXT: s_xor_b64 s[8:9], exec, s[8:9]
|
||||
; CHECK-NEXT: ; mask branch BB0_1
|
||||
; CHECK-NEXT: s_cbranch_execz BB0_1
|
||||
; CHECK-NEXT: ; %bb.5: ; %endif2
|
||||
; CHECK-NEXT: BB0_5: ; %endif2
|
||||
; CHECK-NEXT: ; in Loop: Header=BB0_3 Depth=1
|
||||
; CHECK-NEXT: s_add_i32 s0, s0, 1
|
||||
; CHECK-NEXT: s_xor_b64 s[6:7], exec, -1
|
||||
; CHECK-NEXT: s_branch BB0_1
|
||||
; CHECK-NEXT: ; %bb.6: ; %Flow2
|
||||
; CHECK-NEXT: BB0_6: ; %Flow2
|
||||
; CHECK-NEXT: s_or_b64 exec, exec, s[2:3]
|
||||
; CHECK-NEXT: v_mov_b32_e32 v1, 0
|
||||
; CHECK-NEXT: s_and_saveexec_b64 s[0:1], s[4:5]
|
||||
; CHECK-NEXT: ; %bb.7: ; %if1
|
||||
; CHECK-NEXT: ; mask branch BB0_8
|
||||
; CHECK-NEXT: BB0_7: ; %if1
|
||||
; CHECK-NEXT: v_sqrt_f32_e32 v1, v0
|
||||
; CHECK-NEXT: ; %bb.8: ; %endloop
|
||||
; CHECK-NEXT: BB0_8: ; %endloop
|
||||
; CHECK-NEXT: s_or_b64 exec, exec, s[0:1]
|
||||
; CHECK-NEXT: exp mrt0 v1, v1, v1, v1 done vm
|
||||
; CHECK-NEXT: s_endpgm
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@
|
|||
; CHECK: ; %Flow
|
||||
; CHECK-NEXT: s_or_saveexec_b64 [[DST:s\[[0-9]+:[0-9]+\]]],
|
||||
; CHECK-NEXT: s_xor_b64 exec, exec, [[DST]]
|
||||
; CHECK-NEXT: ; mask branch
|
||||
define amdgpu_ps float @else_no_execfix(i32 %z, float %v) #0 {
|
||||
main_body:
|
||||
%cc = icmp sgt i32 %z, 5
|
||||
|
|
@ -31,7 +32,7 @@ end:
|
|||
; CHECK-NEXT: s_and_b64 exec, exec, [[INIT_EXEC]]
|
||||
; CHECK-NEXT: s_and_b64 [[AND_INIT:s\[[0-9]+:[0-9]+\]]], exec, [[DST]]
|
||||
; CHECK-NEXT: s_xor_b64 exec, exec, [[AND_INIT]]
|
||||
; CHECK-NEXT: s_cbranch_execz
|
||||
; CHECK-NEXT: ; mask branch
|
||||
define amdgpu_ps void @else_execfix_leave_wqm(i32 %z, float %v) #0 {
|
||||
main_body:
|
||||
%cc = icmp sgt i32 %z, 5
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
; CHECK-NOT: v_cmp
|
||||
; CHECK_NOT: v_cndmask
|
||||
; CHECK: s_and_saveexec_b64 s[{{[[0-9]+:[0-9]+}}], [[COND]]
|
||||
; CHECK: ; %bb.2:
|
||||
; CHECK: BB0_2:
|
||||
|
||||
define amdgpu_kernel void @hoist_cond(float addrspace(1)* nocapture %arg, float addrspace(1)* noalias nocapture readonly %arg1, i32 %arg3, i32 %arg4) {
|
||||
bb:
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -march=amdgcn -mcpu=polaris10 -run-pass si-insert-skips -amdgpu-skip-threshold-legacy=1 -verify-machineinstrs %s -o - | FileCheck %s
|
||||
# RUN: llc -march=amdgcn -mcpu=polaris10 -run-pass si-insert-skips -amdgpu-skip-threshold=1 -verify-machineinstrs %s -o - | FileCheck %s
|
||||
|
||||
---
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass si-insert-skips -amdgpu-skip-threshold-legacy=1 -verify-machineinstrs %s -o - | FileCheck %s
|
||||
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass si-insert-skips -amdgpu-skip-threshold=1 -verify-machineinstrs %s -o - | FileCheck %s
|
||||
# Make sure mandatory skips are inserted to ensure GWS ops aren't run with exec = 0
|
||||
|
||||
---
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass si-insert-skips -amdgpu-skip-threshold-legacy=2 %s -o - | FileCheck %s
|
||||
# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass si-insert-skips -amdgpu-skip-threshold=2 %s -o - | FileCheck %s
|
||||
|
||||
---
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
# RUN: llc -march=amdgcn -mcpu=polaris10 -run-pass si-insert-skips -amdgpu-skip-threshold-legacy=1 %s -o - | FileCheck %s
|
||||
# RUN: llc -march=amdgcn -mcpu=polaris10 -run-pass si-insert-skips -amdgpu-skip-threshold=1 %s -o - | FileCheck %s
|
||||
# https://bugs.freedesktop.org/show_bug.cgi?id=99019
|
||||
--- |
|
||||
define amdgpu_ps void @kill_uncond_branch() {
|
||||
|
|
|
|||
|
|
@ -158,7 +158,7 @@ entry:
|
|||
; W64: s_mov_b64 exec, [[SAVEEXEC]]
|
||||
; W64: s_cbranch_execz [[TERMBB:BB[0-9]+_[0-9]+]]
|
||||
|
||||
; W64: ; %bb.{{[0-9]+}}:
|
||||
; W64: BB{{[0-9]+_[0-9]+}}:
|
||||
; W64-DAG: v_mov_b32_e32 [[IDX:v[0-9]+]], s4
|
||||
; W64-DAG: s_mov_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], exec
|
||||
|
||||
|
|
@ -204,7 +204,7 @@ entry:
|
|||
; W32: s_mov_b32 exec_lo, [[SAVEEXEC]]
|
||||
; W32: s_cbranch_execz [[TERMBB:BB[0-9]+_[0-9]+]]
|
||||
|
||||
; W32: ; %bb.{{[0-9]+}}:
|
||||
; W32: BB{{[0-9]+_[0-9]+}}:
|
||||
; W32-DAG: v_mov_b32_e32 [[IDX:v[0-9]+]], s4
|
||||
; W32-DAG: s_mov_b32 [[SAVEEXEC:s[0-9]+]], exec_lo
|
||||
|
||||
|
|
@ -270,7 +270,7 @@ entry:
|
|||
; W64-O0: buffer_store_dword [[RES]], off, s[0:3], s32 offset:[[RES_OFF:[0-9]+]] ; 4-byte Folded Spill
|
||||
; W64-O0: s_cbranch_execz [[TERMBB:BB[0-9]+_[0-9]+]]
|
||||
|
||||
; W64-O0: ; %bb.{{[0-9]+}}:
|
||||
; W64-O0: BB{{[0-9]+_[0-9]+}}:
|
||||
; W64-O0-DAG: s_mov_b64 s{{\[}}[[SAVEEXEC0:[0-9]+]]:[[SAVEEXEC1:[0-9]+]]{{\]}}, exec
|
||||
; W64-O0-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], s32 offset:[[IDX_OFF:[0-9]+]] ; 4-byte Folded Spill
|
||||
; W64-O0: v_writelane_b32 [[VSAVEEXEC:v[0-9]+]], s[[SAVEEXEC0]], [[SAVEEXEC_IDX0:[0-9]+]]
|
||||
|
|
|
|||
|
|
@ -58,8 +58,9 @@ define void @lsr_order_mul24_1(i32 %arg, i32 %arg1, i32 %arg2, float addrspace(3
|
|||
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v5
|
||||
; GFX9-NEXT: v_cmp_lt_u32_e64 s[4:5], v0, v1
|
||||
; GFX9-NEXT: s_and_saveexec_b64 s[10:11], s[4:5]
|
||||
; GFX9-NEXT: ; mask branch BB1_4
|
||||
; GFX9-NEXT: s_cbranch_execz BB1_4
|
||||
; GFX9-NEXT: ; %bb.1: ; %bb19
|
||||
; GFX9-NEXT: BB1_1: ; %bb19
|
||||
; GFX9-NEXT: v_cvt_f32_u32_e32 v7, v6
|
||||
; GFX9-NEXT: v_and_b32_e32 v5, 0xffffff, v6
|
||||
; GFX9-NEXT: v_add_u32_e32 v6, v4, v0
|
||||
|
|
|
|||
|
|
@ -11,11 +11,12 @@
|
|||
; GCN-NEXT: ; %else
|
||||
|
||||
; GCN: s_and_saveexec_b64 [[SAVE_EXEC:s\[[0-9]+:[0-9]+\]]], vcc
|
||||
; GCN-NEXT: ; mask branch [[FLOW:BB[0-9]+_[0-9]+]]
|
||||
|
||||
; GCN: ; %bb.{{[0-9]+}}: ; %unreachable.bb
|
||||
; GCN: BB{{[0-9]+_[0-9]+}}: ; %unreachable.bb
|
||||
; GCN-NEXT: ; divergent unreachable
|
||||
|
||||
; GCN-NEXT: ; %bb.{{[0-9]+}}: ; %Flow
|
||||
; GCN-NEXT: {{^}}[[FLOW]]: ; %Flow
|
||||
; GCN-NEXT: s_or_b64 exec, exec
|
||||
|
||||
; GCN-NEXT: [[RET_BB]]:
|
||||
|
|
@ -54,17 +55,11 @@ ret.bb: ; preds = %else, %main_body
|
|||
}
|
||||
|
||||
; GCN-LABEL: {{^}}uniform_br_nontrivial_ret_divergent_br_nontrivial_unreachable:
|
||||
; GCN: s_cbranch_vccz
|
||||
; GCN: s_cbranch_vccnz [[RET_BB:BB[0-9]+_[0-9]+]]
|
||||
|
||||
; GCN: ; %bb.{{[0-9]+}}: ; %Flow
|
||||
; GCN: s_cbranch_execnz [[RETURN:BB[0-9]+_[0-9]+]]
|
||||
|
||||
; GCN: ; %UnifiedReturnBlock
|
||||
; GCN-NEXT: s_or_b64 exec, exec
|
||||
; GCN-NEXT: s_waitcnt
|
||||
|
||||
; GCN: BB{{[0-9]+_[0-9]+}}: ; %else
|
||||
; GCN: ; %bb.{{[0-9]+}}: ; %else
|
||||
; GCN: s_and_saveexec_b64 [[SAVE_EXEC:s\[[0-9]+:[0-9]+\]]], vcc
|
||||
; GCN-NEXT: ; mask branch [[FLOW1:BB[0-9]+_[0-9]+]]
|
||||
|
||||
; GCN-NEXT: ; %unreachable.bb
|
||||
; GCN: ds_write_b32
|
||||
|
|
@ -72,6 +67,12 @@ ret.bb: ; preds = %else, %main_body
|
|||
|
||||
; GCN: ; %ret.bb
|
||||
; GCN: store_dword
|
||||
|
||||
; GCN: ; %UnifiedReturnBlock
|
||||
; GCN-NEXT: s_or_b64 exec, exec
|
||||
; GCN-NEXT: s_waitcnt
|
||||
; GCN-NEXT: ; return
|
||||
; GCN-NEXT: .Lfunc_end
|
||||
define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @uniform_br_nontrivial_ret_divergent_br_nontrivial_unreachable([9 x <4 x i32>] addrspace(4)* inreg %arg, [17 x <4 x i32>] addrspace(4)* inreg %arg1, [17 x <8 x i32>] addrspace(4)* inreg %arg2, i32 addrspace(4)* inreg %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, i32 inreg %arg18, i32 %arg19, float %arg20, i32 %arg21) #0 {
|
||||
main_body:
|
||||
%i.i = extractelement <2 x i32> %arg7, i32 0
|
||||
|
|
|
|||
|
|
@ -40,6 +40,8 @@ bb5: ; preds = %bb3, %bb1
|
|||
; GCN: load_dwordx4
|
||||
; GCN: v_cmp_nlt_f32
|
||||
; GCN: s_and_saveexec_b64
|
||||
; GCN: ; mask branch [[UNIFIED_RET:BB[0-9]+_[0-9]+]]
|
||||
; GCN-NEXT: [[UNIFIED_RET]]:
|
||||
; GCN-NEXT: s_endpgm
|
||||
; GCN: .Lfunc_end
|
||||
define amdgpu_kernel void @annotate_ret_noloop(<4 x float> addrspace(1)* noalias nocapture readonly %arg) #0 {
|
||||
|
|
|
|||
|
|
@ -3,12 +3,13 @@
|
|||
; GCN-LABEL: {{^}}lower_control_flow_unreachable_terminator:
|
||||
; GCN: v_cmp_eq_u32
|
||||
; GCN: s_and_saveexec_b64
|
||||
; GCN: ; mask branch [[RET:BB[0-9]+_[0-9]+]]
|
||||
|
||||
; GCN-NEXT: ; %bb.{{[0-9]+}}: ; %unreachable
|
||||
; GCN-NEXT: BB{{[0-9]+_[0-9]+}}: ; %unreachable
|
||||
; GCN: ds_write_b32
|
||||
; GCN: ; divergent unreachable
|
||||
|
||||
; GCN-NEXT: ; %bb.{{[0-9]+}}: ; %UnifiedReturnBlock
|
||||
; GCN-NEXT: [[RET]]: ; %UnifiedReturnBlock
|
||||
; GCN: s_endpgm
|
||||
|
||||
define amdgpu_kernel void @lower_control_flow_unreachable_terminator() #0 {
|
||||
|
|
@ -28,12 +29,13 @@ ret:
|
|||
; GCN-LABEL: {{^}}lower_control_flow_unreachable_terminator_swap_block_order:
|
||||
; GCN: v_cmp_ne_u32
|
||||
; GCN: s_and_saveexec_b64
|
||||
; GCN: ; mask branch [[RETURN:BB[0-9]+_[0-9]+]]
|
||||
|
||||
; GCN-NEXT: ; %bb.{{[0-9]+}}: ; %unreachable
|
||||
; GCN-NEXT: {{^BB[0-9]+_[0-9]+}}: ; %unreachable
|
||||
; GCN: ds_write_b32
|
||||
; GCN: ; divergent unreachable
|
||||
|
||||
; GCN: ; %bb.{{[0-9]+}}:
|
||||
; GCN: [[RETURN]]:
|
||||
; GCN-NEXT: s_endpgm
|
||||
define amdgpu_kernel void @lower_control_flow_unreachable_terminator_swap_block_order() #0 {
|
||||
bb:
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@ body: |
|
|||
; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], undef %1:sreg_64, implicit-def dead $scc
|
||||
; GCN: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[S_AND_B64_]], [[COPY]], implicit-def dead $scc
|
||||
; GCN: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
|
||||
; GCN: S_CBRANCH_EXECZ %bb.2, implicit $exec
|
||||
; GCN: SI_MASK_BRANCH %bb.2, implicit $exec
|
||||
; GCN: S_BRANCH %bb.1
|
||||
; GCN: bb.1:
|
||||
; GCN: successors: %bb.2(0x80000000)
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-insert-skips -amdgpu-skip-threshold-legacy=1000000 -o - %s | FileCheck %s
|
||||
# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-insert-skips -amdgpu-skip-threshold=1000000 -o - %s | FileCheck %s
|
||||
|
||||
---
|
||||
name: skip_branch_taildup_endpgm
|
||||
|
|
|
|||
|
|
@ -5,8 +5,9 @@
|
|||
; An s_cbranch_execnz is required to avoid trapping if all lanes are 0
|
||||
; GCN-LABEL: {{^}}trap_divergent_branch:
|
||||
; GCN: s_and_saveexec_b64
|
||||
; GCN: s_cbranch_execnz [[TRAP:BB[0-9]+_[0-9]+]]
|
||||
; GCN: ; %bb.{{[0-9]+}}:
|
||||
; GCN: s_cbranch_execz [[ENDPGM:BB[0-9]+_[0-9]+]]
|
||||
; GCN: s_branch [[TRAP:BB[0-9]+_[0-9]+]]
|
||||
; GCN: [[ENDPGM]]:
|
||||
; GCN-NEXT: s_endpgm
|
||||
; GCN: [[TRAP]]:
|
||||
; GCN: s_trap 2
|
||||
|
|
@ -29,7 +30,7 @@ end:
|
|||
; GCN-LABEL: {{^}}debugtrap_divergent_branch:
|
||||
; GCN: s_and_saveexec_b64
|
||||
; GCN: s_cbranch_execz [[ENDPGM:BB[0-9]+_[0-9]+]]
|
||||
; GCN: ; %bb.{{[0-9]+}}:
|
||||
; GCN: BB{{[0-9]+}}_{{[0-9]+}}:
|
||||
; GCN: s_trap 3
|
||||
; GCN-NEXT: [[ENDPGM]]:
|
||||
; GCN-NEXT: s_endpgm
|
||||
|
|
|
|||
|
|
@ -220,9 +220,10 @@ exit:
|
|||
; CHECK: v_cmp_eq_u32_e32 vcc, 0, v0
|
||||
; CHECK-NEXT: s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], vcc
|
||||
; CHECK-NEXT: s_xor_b64 [[SAVEEXEC]], exec, [[SAVEEXEC]]
|
||||
; CHECK-NEXT: s_cbranch_execz [[EXIT:BB[0-9]+_[0-9]+]]
|
||||
; CHECK-NEXT: ; mask branch [[EXIT:BB[0-9]+_[0-9]+]]
|
||||
; CHECK-NEXT: s_cbranch_execz [[EXIT]]
|
||||
|
||||
; CHECK: ; %bb.{{[0-9]+}}: ; %bb.preheader
|
||||
; CHECK: {{BB[0-9]+_[0-9]+}}: ; %bb.preheader
|
||||
; CHECK: s_mov_b32
|
||||
|
||||
; CHECK: [[LOOP_BB:BB[0-9]+_[0-9]+]]:
|
||||
|
|
@ -356,18 +357,20 @@ bb7: ; preds = %bb4
|
|||
; CHECK: ; %bb.0:
|
||||
; CHECK: s_and_saveexec_b64
|
||||
; CHECK: s_xor_b64
|
||||
; CHECK-NEXT: mask branch [[BB4:BB[0-9]+_[0-9]+]]
|
||||
|
||||
; CHECK: v_cmpx_gt_f32_e32 vcc, 0,
|
||||
; CHECK: BB{{[0-9]+_[0-9]+}}:
|
||||
; CHECK: [[BB4]]:
|
||||
; CHECK: s_or_b64 exec, exec
|
||||
; CHECK: image_sample_c
|
||||
|
||||
; CHECK: v_cmp_neq_f32_e32 vcc, 0,
|
||||
; CHECK: s_and_saveexec_b64 s{{\[[0-9]+:[0-9]+\]}}, vcc
|
||||
; CHECK-NEXT: s_cbranch_execz [[END:BB[0-9]+_[0-9]+]]
|
||||
; CHECK: mask branch [[END:BB[0-9]+_[0-9]+]]
|
||||
; CHECK-NEXT: s_cbranch_execz [[END]]
|
||||
; CHECK-NOT: branch
|
||||
|
||||
; CHECK: ; %bb.{{[0-9]+}}: ; %bb8
|
||||
; CHECK: BB{{[0-9]+_[0-9]+}}: ; %bb8
|
||||
; CHECK: buffer_store_dword
|
||||
|
||||
; CHECK: [[END]]:
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GCN
|
||||
|
||||
; GCN-LABEL: ; %bb.0:
|
||||
; GCN-LABEL: BB0_1
|
||||
; GCN: s_load_dword s{{[0-9]+}}, s{{\[}}[[ADDR_LO:[0-9]+]]{{\:}}[[ADDR_HI:[0-9]+]]{{\]}}, 0x0
|
||||
; GCN: s_waitcnt lgkmcnt(0)
|
||||
; GCN: global_store_dword v{{\[}}[[ADDR_LO]]{{\:}}[[ADDR_HI]]{{\]}}, v{{[0-9]+}}, off
|
||||
|
|
|
|||
|
|
@ -28,8 +28,9 @@ define amdgpu_kernel void @kernel_background_evaluate(float addrspace(5)* %kg, <
|
|||
; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
|
||||
; GCN-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
|
||||
; GCN-NEXT: s_and_saveexec_b32 s0, vcc_lo
|
||||
; GCN-NEXT: ; mask branch BB0_2
|
||||
; GCN-NEXT: s_cbranch_execz BB0_2
|
||||
; GCN-NEXT: ; %bb.1: ; %if.then4.i
|
||||
; GCN-NEXT: BB0_1: ; %if.then4.i
|
||||
; GCN-NEXT: buffer_load_dword v0, v32, s[36:39], s32 offen
|
||||
; GCN-NEXT: buffer_load_dword v1, v32, s[36:39], s32 offen offset:4
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
|
|
|
|||
|
|
@ -18,13 +18,14 @@ define amdgpu_kernel void @foobar(float %a0, float %a1, float addrspace(1)* %out
|
|||
; CHECK-NEXT: v_mov_b32_e32 v2, s6
|
||||
; CHECK-NEXT: v_mov_b32_e32 v3, s7
|
||||
; CHECK-NEXT: s_and_saveexec_b64 s[6:7], vcc
|
||||
; CHECK-NEXT: ; %bb.1: ; %ift
|
||||
; CHECK-NEXT: ; mask branch BB0_2
|
||||
; CHECK-NEXT: BB0_1: ; %ift
|
||||
; CHECK-NEXT: s_mov_b32 s4, s5
|
||||
; CHECK-NEXT: v_mov_b32_e32 v0, s4
|
||||
; CHECK-NEXT: v_mov_b32_e32 v1, s5
|
||||
; CHECK-NEXT: v_mov_b32_e32 v2, s6
|
||||
; CHECK-NEXT: v_mov_b32_e32 v3, s7
|
||||
; CHECK-NEXT: ; %bb.2: ; %ife
|
||||
; CHECK-NEXT: BB0_2: ; %ife
|
||||
; CHECK-NEXT: s_or_b64 exec, exec, s[6:7]
|
||||
; CHECK-NEXT: s_mov_b32 s3, 0xf000
|
||||
; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], 0
|
||||
|
|
|
|||
|
|
@ -335,7 +335,7 @@ endif:
|
|||
; GCN: [[IF_LABEL]]:
|
||||
; GCN: v_cmp_gt_u32_e32 vcc, 16, v{{[0-9]+}}
|
||||
; GCN: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc
|
||||
; GCN: s_cbranch_execz [[ENDIF_LABEL]]
|
||||
; GCN: ; mask branch [[ENDIF_LABEL]]
|
||||
; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
|
||||
; GCN: buffer_store_dword [[ONE]]
|
||||
; GCN: s_endpgm
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@
|
|||
; CHECK-LABEL: {{^}}test1:
|
||||
; CHECK: v_cmp_ne_u32_e32 vcc, 0
|
||||
; CHECK: s_and_saveexec_b64
|
||||
; CHECK-NEXT: ; mask branch
|
||||
; CHECK-NEXT: s_cbranch_execz BB{{[0-9]+_[0-9]+}}
|
||||
|
||||
; CHECK: [[LOOP_BODY_LABEL:BB[0-9]+_[0-9]+]]: ; %loop_body
|
||||
|
|
@ -32,6 +33,7 @@ out:
|
|||
|
||||
; CHECK-LABEL: {{^}}test2:
|
||||
; CHECK: s_and_saveexec_b64
|
||||
; CHECK-NEXT: ; mask branch
|
||||
; CHECK-NEXT: s_cbranch_execz
|
||||
define amdgpu_kernel void @test2(i32 addrspace(1)* %out, i32 %a, i32 %b) {
|
||||
main_body:
|
||||
|
|
|
|||
|
|
@ -13,16 +13,19 @@ declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
|
|||
; SI-NEXT: s_mov_b64 {{s\[[0-9]+:[0-9]+\]}}, 0
|
||||
; SI-NEXT: s_and_saveexec_b64 [[SAVE1:s\[[0-9]+:[0-9]+\]]], vcc
|
||||
; SI-NEXT: s_xor_b64 [[SAVE2:s\[[0-9]+:[0-9]+\]]], exec, [[SAVE1]]
|
||||
; SI-NEXT: ; mask branch [[FLOW_BB:BB[0-9]+_[0-9]+]]
|
||||
; SI-NEXT: s_cbranch_execz [[FLOW_BB]]
|
||||
|
||||
; SI-NEXT: ; %bb.{{[0-9]+}}: ; %LeafBlock3
|
||||
; SI-NEXT: BB{{[0-9]+}}_1: ; %LeafBlock3
|
||||
; SI: s_mov_b64 s[{{[0-9]:[0-9]}}], -1
|
||||
; SI: s_and_saveexec_b64
|
||||
; SI-NEXT: s_cbranch_execnz
|
||||
; SI-NEXT: ; mask branch
|
||||
|
||||
; v_mov should be after exec modification
|
||||
; SI: ; %bb.{{[0-9]+}}:
|
||||
; SI: [[FLOW_BB]]:
|
||||
; SI-NEXT: s_or_saveexec_b64 [[SAVE3:s\[[0-9]+:[0-9]+\]]], [[SAVE2]]
|
||||
; SI-NEXT: s_xor_b64 exec, exec, [[SAVE3]]
|
||||
; SI-NEXT: ; mask branch
|
||||
;
|
||||
define amdgpu_kernel void @test_if(i32 %b, i32 addrspace(1)* %src, i32 addrspace(1)* %dst) #1 {
|
||||
entry:
|
||||
|
|
@ -62,9 +65,10 @@ end:
|
|||
; SI-LABEL: {{^}}simple_test_v_if:
|
||||
; SI: v_cmp_ne_u32_e32 vcc, 0, v{{[0-9]+}}
|
||||
; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc
|
||||
; SI-NEXT: s_cbranch_execz [[EXIT:BB[0-9]+_[0-9]+]]
|
||||
; SI-NEXT: ; mask branch [[EXIT:BB[0-9]+_[0-9]+]]
|
||||
; SI-NEXT: s_cbranch_execz [[EXIT]]
|
||||
|
||||
; SI-NEXT: ; %bb.{{[0-9]+}}:
|
||||
; SI-NEXT: BB{{[0-9]+_[0-9]+}}:
|
||||
; SI: buffer_store_dword
|
||||
|
||||
; SI-NEXT: {{^}}[[EXIT]]:
|
||||
|
|
@ -88,9 +92,10 @@ exit:
|
|||
; SI-LABEL: {{^}}simple_test_v_if_ret_else_ret:
|
||||
; SI: v_cmp_ne_u32_e32 vcc, 0, v{{[0-9]+}}
|
||||
; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc
|
||||
; SI-NEXT: s_cbranch_execz [[EXIT:BB[0-9]+_[0-9]+]]
|
||||
; SI-NEXT: ; mask branch [[EXIT:BB[0-9]+_[0-9]+]]
|
||||
; SI-NEXT: s_cbranch_execz [[EXIT]]
|
||||
|
||||
; SI-NEXT: ; %bb.{{[0-9]+}}:
|
||||
; SI-NEXT: BB{{[0-9]+_[0-9]+}}:
|
||||
; SI: buffer_store_dword
|
||||
|
||||
; SI-NEXT: {{^}}[[EXIT]]:
|
||||
|
|
@ -117,22 +122,23 @@ exit:
|
|||
; SI: v_cmp_eq_u32_e32 vcc, 0, v{{[0-9]+}}
|
||||
; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc
|
||||
; SI: s_xor_b64 [[BR_SREG]], exec, [[BR_SREG]]
|
||||
; SI: s_cbranch_execnz [[EXIT:BB[0-9]+_[0-9]+]]
|
||||
; SI: ; mask branch [[FLOW:BB[0-9]+_[0-9]+]]
|
||||
|
||||
; SI-NEXT: {{^BB[0-9]+_[0-9]+}}: ; %Flow
|
||||
; SI-NEXT: {{^BB[0-9]+_[0-9]+}}: ; %exit
|
||||
; SI: ds_write_b32
|
||||
|
||||
; SI-NEXT: {{^}}[[FLOW]]:
|
||||
; SI-NEXT: s_or_saveexec_b64
|
||||
; SI-NEXT: s_xor_b64 exec, exec
|
||||
; SI-NEXT: s_cbranch_execz [[UNIFIED_RETURN:BB[0-9]+_[0-9]+]]
|
||||
; SI-NEXT: ; mask branch [[UNIFIED_RETURN:BB[0-9]+_[0-9]+]]
|
||||
; SI-NEXT: s_cbranch_execz [[UNIFIED_RETURN]]
|
||||
|
||||
; SI-NEXT: ; %bb.{{[0-9]+}}: ; %then
|
||||
; SI-NEXT: {{^BB[0-9]+_[0-9]+}}: ; %then
|
||||
; SI: s_waitcnt
|
||||
; SI-NEXT: buffer_store_dword
|
||||
|
||||
; SI-NEXT: {{^}}[[UNIFIED_RETURN]]: ; %UnifiedReturnBlock
|
||||
; SI: s_endpgm
|
||||
|
||||
; SI-NEXT: {{^}}[[EXIT]]:
|
||||
; SI: ds_write_b32
|
||||
define amdgpu_kernel void @simple_test_v_if_ret_else_code_ret(i32 addrspace(1)* %dst, i32 addrspace(1)* %src) #1 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%is.0 = icmp ne i32 %tid, 0
|
||||
|
|
@ -151,6 +157,7 @@ exit:
|
|||
; SI-LABEL: {{^}}simple_test_v_loop:
|
||||
; SI: v_cmp_ne_u32_e32 vcc, 0, v{{[0-9]+}}
|
||||
; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc
|
||||
; SI-NEXT: ; mask branch
|
||||
; SI-NEXT: s_cbranch_execz [[LABEL_EXIT:BB[0-9]+_[0-9]+]]
|
||||
|
||||
; SI: s_mov_b64 {{s\[[0-9]+:[0-9]+\]}}, 0{{$}}
|
||||
|
|
@ -192,10 +199,11 @@ exit:
|
|||
; SI: buffer_load_dword [[VBOUND:v[0-9]+]]
|
||||
; SI: v_cmp_lt_i32_e32 vcc
|
||||
; SI: s_and_saveexec_b64 [[OUTER_CMP_SREG:s\[[0-9]+:[0-9]+\]]], vcc
|
||||
; SI-NEXT: ; mask branch
|
||||
; SI-NEXT: s_cbranch_execz [[LABEL_EXIT:BB[0-9]+_[0-9]+]]
|
||||
|
||||
; Initialize inner condition to false
|
||||
; SI: ; %bb.{{[0-9]+}}: ; %bb10.preheader
|
||||
; SI: BB{{[0-9]+_[0-9]+}}: ; %bb10.preheader
|
||||
; SI: s_mov_b64 [[COND_STATE:s\[[0-9]+:[0-9]+\]]], 0{{$}}
|
||||
|
||||
; Clear exec bits for workitems that load -1s
|
||||
|
|
@ -206,9 +214,9 @@ exit:
|
|||
; SI-DAG: v_cmp_ne_u32_e32 [[NEG1_CHECK_1:vcc]], -1, [[B]]
|
||||
; SI: s_and_b64 [[ORNEG1:s\[[0-9]+:[0-9]+\]]], [[NEG1_CHECK_1]], [[NEG1_CHECK_0]]
|
||||
; SI: s_and_saveexec_b64 [[ORNEG2:s\[[0-9]+:[0-9]+\]]], [[ORNEG1]]
|
||||
; SI: s_cbranch_execz [[LABEL_FLOW:BB[0-9]+_[0-9]+]]
|
||||
; SI: ; mask branch [[LABEL_FLOW:BB[0-9]+_[0-9]+]]
|
||||
|
||||
; SI: ; %bb.{{[0-9]+}}: ; %bb20
|
||||
; SI: BB{{[0-9]+_[0-9]+}}: ; %bb20
|
||||
; SI: buffer_store_dword
|
||||
|
||||
; SI: [[LABEL_FLOW]]:
|
||||
|
|
|
|||
|
|
@ -151,7 +151,7 @@ define amdgpu_kernel void @test_vop3_cmp_u32_sop_or(i32 addrspace(1)* %arg) {
|
|||
; GCN-LABEL: {{^}}test_mask_if:
|
||||
; GFX1032: s_and_saveexec_b32 s{{[0-9]+}}, vcc_lo
|
||||
; GFX1064: s_and_saveexec_b64 s[{{[0-9:]+}}], vcc{{$}}
|
||||
; GCN: s_cbranch_execz
|
||||
; GCN: ; mask branch
|
||||
define amdgpu_kernel void @test_mask_if(i32 addrspace(1)* %arg) #0 {
|
||||
%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%cmp = icmp ugt i32 %lid, 10
|
||||
|
|
@ -175,18 +175,19 @@ endif:
|
|||
; GFX1032: s_and_saveexec_b32 s{{[0-9]+}}, vcc_lo
|
||||
; GFX1064: s_and_saveexec_b64 s[{{[0-9:]+}}], vcc{{$}}
|
||||
; GCN: s_cbranch_execz
|
||||
; GCN: ; %bb.{{[0-9]+}}:
|
||||
; GCN: BB{{.*}}:
|
||||
; GCN: BB{{.*}}:
|
||||
; GFX1032: s_xor_b32 s{{[0-9]+}}, exec_lo, s{{[0-9]+}}
|
||||
; GFX1064: s_xor_b64 s[{{[0-9:]+}}], exec, s[{{[0-9:]+}}]
|
||||
; GCN: ; %bb.{{[0-9]+}}:
|
||||
; GCN: ; %bb.{{[0-9]+}}:
|
||||
; GCN: ; mask branch BB
|
||||
; GCN: BB{{.*}}:
|
||||
; GCN: BB{{.*}}:
|
||||
; GFX1032: s_or_b32 exec_lo, exec_lo, s{{[0-9]+}}
|
||||
; GFX1032: s_and_saveexec_b32 s{{[0-9]+}}, s{{[0-9]+}}
|
||||
; GFX1064: s_or_b64 exec, exec, s[{{[0-9:]+}}]
|
||||
; GFX1064: s_and_saveexec_b64 s[{{[0-9:]+}}], s[{{[0-9:]+}}]{{$}}
|
||||
; GCN: s_cbranch_execz BB
|
||||
; GCN: ; %bb.{{[0-9]+}}:
|
||||
; GCN: ; mask branch BB
|
||||
; GCN: BB{{.*}}:
|
||||
; GCN: BB{{.*}}:
|
||||
; GCN: s_endpgm
|
||||
define amdgpu_kernel void @test_loop_with_if(i32 addrspace(1)* %arg) #0 {
|
||||
|
|
@ -227,8 +228,9 @@ bb13:
|
|||
; GCN-LABEL: {{^}}test_loop_with_if_else_break:
|
||||
; GFX1032: s_and_saveexec_b32 s{{[0-9]+}}, vcc_lo
|
||||
; GFX1064: s_and_saveexec_b64 s[{{[0-9:]+}}], vcc{{$}}
|
||||
; GCN: ; mask branch
|
||||
; GCN: s_cbranch_execz
|
||||
; GCN: ; %bb.{{[0-9]+}}: ; %.preheader
|
||||
; GCN: BB{{.*}}:
|
||||
; GCN: BB{{.*}}:
|
||||
|
||||
; GFX1032: s_or_b32 [[MASK0:s[0-9]+]], [[MASK0]], vcc_lo
|
||||
|
|
|
|||
|
|
@ -425,8 +425,9 @@ END:
|
|||
;CHECK-NEXT: s_and_b64 exec, exec, [[ORIG]]
|
||||
;CHECK-NEXT: s_and_b64 [[SAVED]], exec, [[SAVED]]
|
||||
;CHECK-NEXT: s_xor_b64 exec, exec, [[SAVED]]
|
||||
;CHECK-NEXT: s_cbranch_execz [[END_BB:BB[0-9]+_[0-9]+]]
|
||||
;CHECK-NEXT: ; %bb.{{[0-9]+}}: ; %ELSE
|
||||
;CHECK-NEXT: mask branch [[END_BB:BB[0-9]+_[0-9]+]]
|
||||
;CHECK-NEXT: s_cbranch_execz [[END_BB]]
|
||||
;CHECK-NEXT: BB{{[0-9]+_[0-9]+}}: ; %ELSE
|
||||
;CHECK: store_dword
|
||||
;CHECK: [[END_BB]]: ; %END
|
||||
;CHECK: s_or_b64 exec, exec,
|
||||
|
|
|
|||
Loading…
Reference in New Issue