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[GlobalISel][IRTranslator] Change the ownership of the MIRBuilder field. 

llvm-svn: 260551
This commit is contained in:
Quentin Colombet 2016-02-11 17:53:23 +00:00
parent 4f0ec8d2b0
commit a7fae162e6
2 changed files with 10 additions and 12 deletions
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4
llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
View File

@ -22,6 +22,7 @@
#include "Types.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
namespace llvm {
@ -32,7 +33,6 @@ class Instruction;
class MachineBasicBlock;
class MachineFunction;
class MachineInstr;
class MachineIRBuilder;
class MachineRegisterInfo;
// Technically the pass should run on an hypothetical MachineModule,
@ -96,7 +96,7 @@ private:
// I.e., compared to regular MIBuilder, this one also inserts the instruction
// in the current block, it can creates block, etc., basically a kind of
// IRBuilder, but for Machine IR.
MachineIRBuilder *MIRBuilder;
MachineIRBuilder MIRBuilder;
/// MachineRegisterInfo used to create virtual registers.
MachineRegisterInfo *MRI;

18
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
View File

@ -12,7 +12,6 @@
#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/IR/Constant.h"
@ -26,6 +25,9 @@ using namespace llvm;
char IRTranslator::ID = 0;
IRTranslator::IRTranslator() : MachineFunctionPass(ID), MRI(nullptr) {
}
const VRegsSequence &IRTranslator::getOrCreateVRegs(const Value *Val) {
VRegsSequence &ValRegSequence = ValToVRegs[Val];
// Check if this is the first time we see Val.
@ -48,7 +50,7 @@ const VRegsSequence &IRTranslator::getOrCreateVRegs(const Value *Val) {
MachineBasicBlock &IRTranslator::getOrCreateBB(const BasicBlock *BB) {
MachineBasicBlock *&MBB = BBToMBB[BB];
if (!MBB) {
MachineFunction &MF = MIRBuilder->getMF();
MachineFunction &MF = MIRBuilder.getMF();
MBB = MF.CreateMachineBasicBlock();
MF.push_back(MBB);
}
@ -63,12 +65,12 @@ bool IRTranslator::translateADD(const Instruction &Inst) {
unsigned Op0 = *getOrCreateVRegs(Inst.getOperand(0)).begin();
unsigned Op1 = *getOrCreateVRegs(Inst.getOperand(1)).begin();
unsigned Res = *getOrCreateVRegs(&Inst).begin();
MIRBuilder->buildInstr(TargetOpcode::G_ADD, Res, Op0, Op1);
MIRBuilder.buildInstr(TargetOpcode::G_ADD, Res, Op0, Op1);
return true;
}
bool IRTranslator::translate(const Instruction &Inst) {
MIRBuilder->setDebugLoc(Inst.getDebugLoc());
MIRBuilder.setDebugLoc(Inst.getDebugLoc());
switch(Inst.getOpcode()) {
case Instruction::Add: {
return translateADD(Inst);
@ -86,17 +88,13 @@ void IRTranslator::finalize() {
Constants.clear();
}
IRTranslator::IRTranslator()
: MachineFunctionPass(ID) {
}
bool IRTranslator::runOnMachineFunction(MachineFunction &MF) {
const Function &F = *MF.getFunction();
MIRBuilder->setFunction(MF);
MIRBuilder.setFunction(MF);
MRI = &MF.getRegInfo();
for (const BasicBlock &BB: F) {
MachineBasicBlock &MBB = getOrCreateBB(&BB);
MIRBuilder->setBasicBlock(MBB);
MIRBuilder.setBasicBlock(MBB);
for (const Instruction &Inst: BB) {
bool Succeeded = translate(Inst);
if (!Succeeded) {