forked from OSchip/llvm-project
[RISCV] Add attribute support for all supported extensions
This adds support for ".attribute arch" for all extensions that are currently supported by the compiler. Differential Revision: https://reviews.llvm.org/D94931
This commit is contained in:
Simon Cook
parent
666815d61b
commit
a7c1239f37
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@ -1997,7 +1997,33 @@ bool RISCVAsmParser::parseDirectiveAttribute() {
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else
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return Error(ValueExprLoc, "bad arch string " + Arch);
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// .attribute arch overrides the current architecture, so unset all
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// currently enabled extensions
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clearFeatureBits(RISCV::FeatureRV32E, "e");
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clearFeatureBits(RISCV::FeatureStdExtM, "m");
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clearFeatureBits(RISCV::FeatureStdExtA, "a");
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clearFeatureBits(RISCV::FeatureStdExtF, "f");
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clearFeatureBits(RISCV::FeatureStdExtD, "d");
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clearFeatureBits(RISCV::FeatureStdExtC, "c");
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clearFeatureBits(RISCV::FeatureStdExtB, "experimental-b");
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clearFeatureBits(RISCV::FeatureStdExtV, "experimental-v");
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clearFeatureBits(RISCV::FeatureExtZfh, "experimental-zfh");
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clearFeatureBits(RISCV::FeatureExtZba, "experimental-zba");
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clearFeatureBits(RISCV::FeatureExtZbb, "experimental-zbb");
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clearFeatureBits(RISCV::FeatureExtZbc, "experimental-zbc");
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clearFeatureBits(RISCV::FeatureExtZbe, "experimental-zbe");
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clearFeatureBits(RISCV::FeatureExtZbf, "experimental-zbf");
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clearFeatureBits(RISCV::FeatureExtZbm, "experimental-zbm");
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clearFeatureBits(RISCV::FeatureExtZbp, "experimental-zbp");
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clearFeatureBits(RISCV::FeatureExtZbproposedc, "experimental-zbproposedc");
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clearFeatureBits(RISCV::FeatureExtZbr, "experimental-zbr");
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clearFeatureBits(RISCV::FeatureExtZbs, "experimental-zbs");
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clearFeatureBits(RISCV::FeatureExtZbt, "experimental-zbt");
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clearFeatureBits(RISCV::FeatureExtZvamo, "experimental-zvamo");
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clearFeatureBits(RISCV::FeatureStdExtZvlsseg, "experimental-zvlsseg");
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while (!Arch.empty()) {
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bool DropFirst = true;
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if (Arch[0] == 'i')
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clearFeatureBits(RISCV::FeatureRV32E, "e");
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else if (Arch[0] == 'e')
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@ -2019,19 +2045,57 @@ bool RISCVAsmParser::parseDirectiveAttribute() {
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setFeatureBits(RISCV::FeatureStdExtD, "d");
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} else if (Arch[0] == 'c') {
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setFeatureBits(RISCV::FeatureStdExtC, "c");
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} else if (Arch[0] == 'b') {
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setFeatureBits(RISCV::FeatureStdExtB, "experimental-b");
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} else if (Arch[0] == 'v') {
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setFeatureBits(RISCV::FeatureStdExtV, "experimental-v");
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} else if (Arch[0] == 's' || Arch[0] == 'x' || Arch[0] == 'z') {
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StringRef Ext =
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Arch.take_until([](char c) { return ::isdigit(c) || c == '_'; });
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if (Ext == "zba")
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setFeatureBits(RISCV::FeatureExtZba, "experimental-zba");
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else if (Ext == "zbb")
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setFeatureBits(RISCV::FeatureExtZbb, "experimental-zbb");
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else if (Ext == "zbc")
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setFeatureBits(RISCV::FeatureExtZbc, "experimental-zbc");
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else if (Ext == "zbe")
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setFeatureBits(RISCV::FeatureExtZbe, "experimental-zbe");
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else if (Ext == "zbf")
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setFeatureBits(RISCV::FeatureExtZbf, "experimental-zbf");
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else if (Ext == "zbm")
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setFeatureBits(RISCV::FeatureExtZbm, "experimental-zbm");
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else if (Ext == "zbp")
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setFeatureBits(RISCV::FeatureExtZbp, "experimental-zbp");
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else if (Ext == "zbproposedc")
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setFeatureBits(RISCV::FeatureExtZbproposedc,
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"experimental-zbproposedc");
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else if (Ext == "zbr")
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setFeatureBits(RISCV::FeatureExtZbr, "experimental-zbr");
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else if (Ext == "zbs")
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setFeatureBits(RISCV::FeatureExtZbs, "experimental-zbs");
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else if (Ext == "zbt")
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setFeatureBits(RISCV::FeatureExtZbt, "experimental-zbt");
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else if (Ext == "zfh")
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setFeatureBits(RISCV::FeatureExtZfh, "experimental-zfh");
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else if (Ext == "zvamo")
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setFeatureBits(RISCV::FeatureExtZvamo, "experimental-zvamo");
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else if (Ext == "zvlsseg")
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setFeatureBits(RISCV::FeatureStdExtZvlsseg, "experimental-zvlsseg");
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else
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return Error(ValueExprLoc, "bad arch string " + Ext);
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Arch = Arch.drop_until([](char c) { return ::isdigit(c) || c == '_'; });
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DropFirst = false;
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} else
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return Error(ValueExprLoc, "bad arch string " + Arch);
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Arch = Arch.drop_front(1);
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if (DropFirst)
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Arch = Arch.drop_front(1);
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int major = 0;
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int minor = 0;
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Arch.consumeInteger(10, major);
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Arch.consume_front("p");
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Arch.consumeInteger(10, minor);
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if (major != 0 || minor != 0) {
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Arch = Arch.drop_until([](char c) { return c == '_' || c == '"'; });
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Arch = Arch.drop_while([](char c) { return c == '_'; });
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}
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Arch = Arch.drop_while([](char c) { return c == '_'; });
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}
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}
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@ -2059,6 +2123,38 @@ bool RISCVAsmParser::parseDirectiveAttribute() {
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formalArchStr = (Twine(formalArchStr) + "_d2p0").str();
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if (getFeatureBits(RISCV::FeatureStdExtC))
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formalArchStr = (Twine(formalArchStr) + "_c2p0").str();
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if (getFeatureBits(RISCV::FeatureStdExtB))
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formalArchStr = (Twine(formalArchStr) + "_b0p93").str();
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if (getFeatureBits(RISCV::FeatureStdExtV))
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formalArchStr = (Twine(formalArchStr) + "_v0p9").str();
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if (getFeatureBits(RISCV::FeatureExtZfh))
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formalArchStr = (Twine(formalArchStr) + "_zfh0p1").str();
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if (getFeatureBits(RISCV::FeatureExtZba))
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formalArchStr = (Twine(formalArchStr) + "_zba0p93").str();
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if (getFeatureBits(RISCV::FeatureExtZbb))
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formalArchStr = (Twine(formalArchStr) + "_zbb0p93").str();
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if (getFeatureBits(RISCV::FeatureExtZbc))
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formalArchStr = (Twine(formalArchStr) + "_zbc0p93").str();
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if (getFeatureBits(RISCV::FeatureExtZbe))
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formalArchStr = (Twine(formalArchStr) + "_zbe0p93").str();
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if (getFeatureBits(RISCV::FeatureExtZbf))
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formalArchStr = (Twine(formalArchStr) + "_zbf0p93").str();
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if (getFeatureBits(RISCV::FeatureExtZbm))
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formalArchStr = (Twine(formalArchStr) + "_zbm0p93").str();
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if (getFeatureBits(RISCV::FeatureExtZbp))
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formalArchStr = (Twine(formalArchStr) + "_zbp0p93").str();
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if (getFeatureBits(RISCV::FeatureExtZbproposedc))
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formalArchStr = (Twine(formalArchStr) + "_zbproposedc0p93").str();
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if (getFeatureBits(RISCV::FeatureExtZbr))
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formalArchStr = (Twine(formalArchStr) + "_zbr0p93").str();
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if (getFeatureBits(RISCV::FeatureExtZbs))
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formalArchStr = (Twine(formalArchStr) + "_zbs0p93").str();
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if (getFeatureBits(RISCV::FeatureExtZbt))
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formalArchStr = (Twine(formalArchStr) + "_zbt0p93").str();
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if (getFeatureBits(RISCV::FeatureExtZvamo))
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formalArchStr = (Twine(formalArchStr) + "_zvamo0p9").str();
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if (getFeatureBits(RISCV::FeatureStdExtZvlsseg))
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formalArchStr = (Twine(formalArchStr) + "_zvlsseg0p9").str();
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getTargetStreamer().emitTextAttribute(Tag, formalArchStr);
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}
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@ -60,6 +60,38 @@ void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
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Arch += "_d2p0";
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if (STI.hasFeature(RISCV::FeatureStdExtC))
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Arch += "_c2p0";
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if (STI.hasFeature(RISCV::FeatureStdExtB))
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Arch += "_b0p93";
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if (STI.hasFeature(RISCV::FeatureStdExtV))
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Arch += "_v0p9";
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if (STI.hasFeature(RISCV::FeatureExtZfh))
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Arch += "_zfh0p1";
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if (STI.hasFeature(RISCV::FeatureExtZba))
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Arch += "_zba0p93";
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if (STI.hasFeature(RISCV::FeatureExtZbb))
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Arch += "_zbb0p93";
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if (STI.hasFeature(RISCV::FeatureExtZbc))
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Arch += "_zbc0p93";
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if (STI.hasFeature(RISCV::FeatureExtZbe))
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Arch += "_zbe0p93";
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if (STI.hasFeature(RISCV::FeatureExtZbf))
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Arch += "_zbf0p93";
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if (STI.hasFeature(RISCV::FeatureExtZbm))
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Arch += "_zbm0p93";
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if (STI.hasFeature(RISCV::FeatureExtZbp))
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Arch += "_zbp0p93";
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if (STI.hasFeature(RISCV::FeatureExtZbproposedc))
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Arch += "_zbproposedc0p93";
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if (STI.hasFeature(RISCV::FeatureExtZbr))
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Arch += "_zbr0p93";
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if (STI.hasFeature(RISCV::FeatureExtZbs))
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Arch += "_zbs0p93";
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if (STI.hasFeature(RISCV::FeatureExtZbt))
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Arch += "_zbt0p93";
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if (STI.hasFeature(RISCV::FeatureExtZvamo))
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Arch += "_zvamo0p9";
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if (STI.hasFeature(RISCV::FeatureStdExtZvlsseg))
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Arch += "_zvlsseg0p9";
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emitTextAttribute(RISCVAttrs::ARCH, Arch);
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}
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@ -5,22 +5,84 @@
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; RUN: llc -mtriple=riscv32 -mattr=+f %s -o - | FileCheck --check-prefix=RV32F %s
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; RUN: llc -mtriple=riscv32 -mattr=+d %s -o - | FileCheck --check-prefix=RV32D %s
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; RUN: llc -mtriple=riscv32 -mattr=+c %s -o - | FileCheck --check-prefix=RV32C %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-b %s -o - | FileCheck --check-prefix=RV32B %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+experimental-zvamo,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32V %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh %s -o - | FileCheck --check-prefix=RV32ZFH %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zba %s -o - | FileCheck --check-prefix=RV32ZBA %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb %s -o - | FileCheck --check-prefix=RV32ZBB %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbc %s -o - | FileCheck --check-prefix=RV32ZBC %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbe %s -o - | FileCheck --check-prefix=RV32ZBE %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbf %s -o - | FileCheck --check-prefix=RV32ZBF %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbm %s -o - | FileCheck --check-prefix=RV32ZBM %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp %s -o - | FileCheck --check-prefix=RV32ZBP %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbproposedc %s -o - | FileCheck --check-prefix=RV32ZBPROPOSEDC %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV32ZBR %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
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; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
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; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
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; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
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; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefix=RV64D %s
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; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefix=RV64C %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-b %s -o - | FileCheck --check-prefix=RV64B %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+experimental-zvamo,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV64V %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh %s -o - | FileCheck --check-prefix=RV64ZFH %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zba %s -o - | FileCheck --check-prefix=RV64ZBA %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb %s -o - | FileCheck --check-prefix=RV64ZBB %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbc %s -o - | FileCheck --check-prefix=RV64ZBC %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbe %s -o - | FileCheck --check-prefix=RV64ZBE %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbf %s -o - | FileCheck --check-prefix=RV64ZBF %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbm %s -o - | FileCheck --check-prefix=RV64ZBM %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp %s -o - | FileCheck --check-prefix=RV64ZBP %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbproposedc %s -o - | FileCheck --check-prefix=RV64ZBPROPOSEDC %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV64ZBR %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV64ZBS %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV64ZBT %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV64COMBINED %s
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; RV32M: .attribute 5, "rv32i2p0_m2p0"
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; RV32A: .attribute 5, "rv32i2p0_a2p0"
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; RV32F: .attribute 5, "rv32i2p0_f2p0"
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; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
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; RV32C: .attribute 5, "rv32i2p0_c2p0"
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; RV32B: .attribute 5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
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; RV32V: .attribute 5, "rv32i2p0_v0p9_zvamo0p9_zvlsseg0p9"
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; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1"
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; RV32ZBA: .attribute 5, "rv32i2p0_zba0p93"
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; RV32ZBB: .attribute 5, "rv32i2p0_zbb0p93"
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; RV32ZBC: .attribute 5, "rv32i2p0_zbc0p93"
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; RV32ZBE: .attribute 5, "rv32i2p0_zbe0p93"
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; RV32ZBF: .attribute 5, "rv32i2p0_zbf0p93"
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; RV32ZBM: .attribute 5, "rv32i2p0_zbm0p93"
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; RV32ZBP: .attribute 5, "rv32i2p0_zbp0p93"
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; RV32ZBPROPOSEDC: .attribute 5, "rv32i2p0_zbproposedc0p93"
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; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
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; RV32ZBS: .attribute 5, "rv32i2p0_zbs0p93"
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; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
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; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p9_zfh0p1_zbb0p93_zvamo0p9_zvlsseg0p9"
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; RV64M: .attribute 5, "rv64i2p0_m2p0"
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; RV64A: .attribute 5, "rv64i2p0_a2p0"
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; RV64F: .attribute 5, "rv64i2p0_f2p0"
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; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0"
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; RV64C: .attribute 5, "rv64i2p0_c2p0"
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; RV64B: .attribute 5, "rv64i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
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; RV64ZFH: .attribute 5, "rv64i2p0_f2p0_zfh0p1"
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; RV64ZBA: .attribute 5, "rv64i2p0_zba0p93"
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; RV64ZBB: .attribute 5, "rv64i2p0_zbb0p93"
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; RV64ZBC: .attribute 5, "rv64i2p0_zbc0p93"
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; RV64ZBE: .attribute 5, "rv64i2p0_zbe0p93"
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; RV64ZBF: .attribute 5, "rv64i2p0_zbf0p93"
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; RV64ZBM: .attribute 5, "rv64i2p0_zbm0p93"
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; RV64ZBP: .attribute 5, "rv64i2p0_zbp0p93"
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; RV64ZBPROPOSEDC: .attribute 5, "rv64i2p0_zbproposedc0p93"
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; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93"
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; RV64ZBS: .attribute 5, "rv64i2p0_zbs0p93"
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; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
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; RV64V: .attribute 5, "rv64i2p0_v0p9_zvamo0p9_zvlsseg0p9"
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; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p9_zfh0p1_zbb0p93_zvamo0p9_zvlsseg0p9"
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define i32 @addi(i32 %a) {
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%1 = add i32 %a, 1
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@ -35,3 +35,51 @@
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.attribute arch, "rv32ima2p_fdc"
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# CHECK: attribute 5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
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.attribute arch, "rv32ib"
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# CHECK: attribute 5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
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.attribute arch, "rv32iv"
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# CHECK: attribute 5, "rv32i2p0_v0p9"
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.attribute arch, "rv32izba"
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# CHECK: attribute 5, "rv32i2p0_zba0p93"
|
||||
|
||||
.attribute arch, "rv32izbb"
|
||||
# CHECK: attribute 5, "rv32i2p0_zbb0p93"
|
||||
|
||||
.attribute arch, "rv32izbc"
|
||||
# CHECK: attribute 5, "rv32i2p0_zbc0p93"
|
||||
|
||||
.attribute arch, "rv32izbe"
|
||||
# CHECK: attribute 5, "rv32i2p0_zbe0p93"
|
||||
|
||||
.attribute arch, "rv32izbf"
|
||||
# CHECK: attribute 5, "rv32i2p0_zbf0p93"
|
||||
|
||||
.attribute arch, "rv32izbm"
|
||||
# CHECK: attribute 5, "rv32i2p0_zbm0p93"
|
||||
|
||||
.attribute arch, "rv32izbp"
|
||||
# CHECK: attribute 5, "rv32i2p0_zbp0p93"
|
||||
|
||||
.attribute arch, "rv32izbproposedc"
|
||||
# CHECK: attribute 5, "rv32i2p0_zbproposedc0p93"
|
||||
|
||||
.attribute arch, "rv32izbr"
|
||||
# CHECK: attribute 5, "rv32i2p0_zbr0p93"
|
||||
|
||||
.attribute arch, "rv32izbs"
|
||||
# CHECK: attribute 5, "rv32i2p0_zbs0p93"
|
||||
|
||||
.attribute arch, "rv32izbt"
|
||||
# CHECK: attribute 5, "rv32i2p0_zbt0p93"
|
||||
|
||||
.attribute arch, "rv32ifzfh"
|
||||
# CHECK: attribute 5, "rv32i2p0_f2p0_zfh0p1"
|
||||
|
||||
.attribute arch, "rv32ivzvamo_zvlsseg"
|
||||
# CHECK: attribute 5, "rv32i2p0_v0p9_zvamo0p9_zvlsseg0p9"
|
||||
|
||||
.attribute arch, "rv32iv_zvamo0p9_zvlsseg"
|
||||
# CHECK: attribute 5, "rv32i2p0_v0p9_zvamo0p9_zvlsseg0p9"
|
||||
|
|
|
|||
Loading…
Reference in New Issue