forked from OSchip/llvm-project
[AArch64][GlobalISel] Implement custom legalization for s32/s64 G_FCOPYSIGN
This is intended to be equivalent to the s32 + s64 cases in AArch64TargetLowering::LowerFCOPYSIGN. Widen everything and then use G_BIT + a mask to handle the actual copysign operation. Then, narrow back down to s32/s64. I wasn't sure about what the best/most canonical INSERT_SUBREG-selectable pattern is. I chose G_INSERT_VECTOR_ELT + an undef vector because it produces reasonably okay codegen. (It doesn't produce INSERT_SUBREG right now though.) If there's a better way to do this then I'm happy to change it. We also have a couple codegen deficiencies with how we emit vector constants right now. (We need a GISel equivalent to the tryAdvSIMDModImm64 stuff) Differential Revision: https://reviews.llvm.org/D108725
This commit is contained in:
Jessica Paquette
parent
ba9cc6537c
commit
a7aaafde2e
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@ -814,6 +814,11 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
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getActionDefinitionsBuilder({G_LROUND, G_LLROUND})
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.legalFor({{s64, s32}, {s64, s64}});
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// TODO: Custom legalization for vector types.
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// TODO: Custom legalization for mismatched types.
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// TODO: s16 support.
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getActionDefinitionsBuilder(G_FCOPYSIGN).customFor({{s32, s32}, {s64, s64}});
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getLegacyLegalizerInfo().computeTables();
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verify(*ST.getInstrInfo());
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}
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@ -856,6 +861,8 @@ bool AArch64LegalizerInfo::legalizeCustom(LegalizerHelper &Helper,
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case TargetOpcode::G_MEMMOVE:
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case TargetOpcode::G_MEMSET:
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return legalizeMemOps(MI, Helper);
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case TargetOpcode::G_FCOPYSIGN:
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return legalizeFCopySign(MI, Helper);
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}
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llvm_unreachable("expected switch to return");
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@ -1438,3 +1445,63 @@ bool AArch64LegalizerInfo::legalizeMemOps(MachineInstr &MI,
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return false;
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}
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bool AArch64LegalizerInfo::legalizeFCopySign(MachineInstr &MI,
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LegalizerHelper &Helper) const {
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MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
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MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
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Register Dst = MI.getOperand(0).getReg();
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LLT DstTy = MRI.getType(Dst);
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assert(DstTy.isScalar() && "Only expected scalars right now!");
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const unsigned DstSize = DstTy.getSizeInBits();
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assert((DstSize == 32 || DstSize == 64) && "Unexpected dst type!");
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assert(MRI.getType(MI.getOperand(2).getReg()) == DstTy &&
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"Expected homogeneous types!");
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// We want to materialize a mask with the high bit set.
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uint64_t EltMask;
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LLT VecTy;
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// TODO: s16 support.
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switch (DstSize) {
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default:
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llvm_unreachable("Unexpected type for G_FCOPYSIGN!");
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case 64: {
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// AdvSIMD immediate moves cannot materialize out mask in a single
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// instruction for 64-bit elements. Instead, materialize zero and then
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// negate it.
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EltMask = 0;
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VecTy = LLT::fixed_vector(2, DstTy);
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break;
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}
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case 32:
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EltMask = 0x80000000ULL;
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VecTy = LLT::fixed_vector(4, DstTy);
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break;
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}
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// Widen In1 and In2 to 128 bits. We want these to eventually become
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// INSERT_SUBREGs.
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auto Undef = MIRBuilder.buildUndef(VecTy);
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auto Zero = MIRBuilder.buildConstant(DstTy, 0);
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auto Ins1 = MIRBuilder.buildInsertVectorElement(
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VecTy, Undef, MI.getOperand(1).getReg(), Zero);
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auto Ins2 = MIRBuilder.buildInsertVectorElement(
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VecTy, Undef, MI.getOperand(2).getReg(), Zero);
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// Construct the mask.
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auto Mask = MIRBuilder.buildConstant(VecTy, EltMask);
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if (DstSize == 64)
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Mask = MIRBuilder.buildFNeg(VecTy, Mask);
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auto Sel = MIRBuilder.buildInstr(AArch64::G_BIT, {VecTy}, {Ins1, Ins2, Mask});
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// Build an unmerge whose 0th elt is the original G_FCOPYSIGN destination. We
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// want this to eventually become an EXTRACT_SUBREG.
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SmallVector<Register, 2> DstRegs(1, Dst);
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for (unsigned I = 1, E = VecTy.getNumElements(); I < E; ++I)
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DstRegs.push_back(MRI.createGenericVirtualRegister(DstTy));
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MIRBuilder.buildUnmerge(DstRegs, Sel);
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MI.eraseFromParent();
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return true;
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}
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@ -57,6 +57,7 @@ private:
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LegalizerHelper &Helper) const;
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bool legalizeCTTZ(MachineInstr &MI, LegalizerHelper &Helper) const;
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bool legalizeMemOps(MachineInstr &MI, LegalizerHelper &Helper) const;
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bool legalizeFCopySign(MachineInstr &MI, LegalizerHelper &Helper) const;
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const AArch64Subtarget *ST;
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};
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} // End llvm namespace.
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@ -0,0 +1,56 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
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...
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---
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name: legalize_s32
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $s0, $s1
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; CHECK-LABEL: name: legalize_s32
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; CHECK: liveins: $s0, $s1
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; CHECK: %val:_(s32) = COPY $s0
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; CHECK: %sign:_(s32) = COPY $s1
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; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], %val(s32), [[C]](s32)
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; CHECK: [[IVEC1:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], %sign(s32), [[C]](s32)
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32)
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; CHECK: [[BIT:%[0-9]+]]:_(<4 x s32>) = G_BIT [[IVEC]], [[IVEC1]], [[BUILD_VECTOR]]
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; CHECK: %fcopysign:_(s32), %10:_(s32), %11:_(s32), %12:_(s32) = G_UNMERGE_VALUES [[BIT]](<4 x s32>)
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; CHECK: $s0 = COPY %fcopysign(s32)
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; CHECK: RET_ReallyLR implicit $s0
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%val:_(s32) = COPY $s0
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%sign:_(s32) = COPY $s1
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%fcopysign:_(s32) = G_FCOPYSIGN %val, %sign(s32)
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$s0 = COPY %fcopysign(s32)
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RET_ReallyLR implicit $s0
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...
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---
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name: legalize_s64
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $d1
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; CHECK-LABEL: name: legalize_s64
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; CHECK: liveins: $d0, $d1
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; CHECK: %val:_(s64) = COPY $d0
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; CHECK: %sign:_(s64) = COPY $d1
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; CHECK: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; CHECK: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], %val(s64), [[C]](s64)
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; CHECK: [[IVEC1:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], %sign(s64), [[C]](s64)
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
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; CHECK: [[FNEG:%[0-9]+]]:_(<2 x s64>) = G_FNEG [[BUILD_VECTOR]]
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; CHECK: [[BIT:%[0-9]+]]:_(<2 x s64>) = G_BIT [[IVEC]], [[IVEC1]], [[FNEG]]
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; CHECK: %fcopysign:_(s64), %10:_(s64) = G_UNMERGE_VALUES [[BIT]](<2 x s64>)
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; CHECK: $d0 = COPY %fcopysign(s64)
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; CHECK: RET_ReallyLR implicit $d0
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%val:_(s64) = COPY $d0
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%sign:_(s64) = COPY $d1
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%fcopysign:_(s64) = G_FCOPYSIGN %val, %sign(s64)
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$d0 = COPY %fcopysign(s64)
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RET_ReallyLR implicit $d0
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@ -487,8 +487,8 @@
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# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: G_FCOPYSIGN (opcode {{[0-9]+}}): 2 type indices
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# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
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# DEBUG-NEXT: .. the first uncovered type index: 2, OK
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# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
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# DEBUG-NEXT: G_IS_FPCLASS (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
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# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
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