forked from OSchip/llvm-project
[RegAllocGreedy] Introduce a late pass to repair broken hints.
A broken hint is a copy where both ends are assigned different colors. When a variable gets evicted in the neighborhood of such copies, it is likely we can reconcile some of them. ** Context ** Copies are inserted during the register allocation via splitting. These split points are required to relax the constraints on the allocation problem. When such a point is inserted, both ends of the copy would not share the same color with respect to the current allocation problem. When variables get evicted, the allocation problem becomes different and some split point may not be required anymore. However, the related variables may already have been colored. This usually shows up in the assembly with pattern like this: def A ... save A to B def A use A restore A from B ... use B Whereas we could simply have done: def B ... def A use A ... use B ** Proposed Solution ** A variable having a broken hint is marked for late recoloring if and only if selecting a register for it evict another variable. Indeed, if no eviction happens this is pointless to look for recoloring opportunities as it means the situation was the same as the initial allocation problem where we had to break the hint. Finally, when everything has been allocated, we look for recoloring opportunities for all the identified candidates. The recoloring is performed very late to rely on accurate copy cost (all involved variables are allocated). The recoloring is simple unlike the last change recoloring. It propagates the color of the broken hint to all its copy-related variables. If the color is available for them, the recoloring uses it, otherwise it gives up on that hint even if a more complex coloring would have worked. The recoloring happens only if it is profitable. The profitability is evaluated using the expected frequency of the copies of the currently recolored variable with a) its current color and b) with the target color. If a) is greater or equal than b), then it is profitable and the recoloring happen. ** Example ** Consider the following example: BB1: a = b = BB2: ... = b = a Let us assume b gets split: BB1: a = b = BB2: c = b ... d = c = d = a Because of how the allocation work, b, c, and d may be assigned different colors. Now, if a gets evicted to make room for c, assuming b and d were assigned to something different than a. We end up with: BB1: a = st a, SpillSlot b = BB2: c = b ... d = c = d e = ld SpillSlot = e This is likely that we can assign the same register for b, c, and d, getting rid of 2 copies. ** Performances ** Both ARM64 and x86_64 show performance improvements of up to 3% for the llvm-testsuite + externals with Os and O3. There are a few regressions too that comes from the (in)accuracy of the block frequency estimate. <rdar://problem/18312047> llvm-svn: 225422
This commit is contained in:
Quentin Colombet
parent
2b6917b020
commit
a799e2e014
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@ -90,6 +90,7 @@ void RegAllocBase::allocatePhysRegs() {
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// Unused registers can appear when the spiller coalesces snippets.
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if (MRI->reg_nodbg_empty(VirtReg->reg)) {
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DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n');
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aboutToRemoveInterval(*VirtReg);
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LIS->removeInterval(VirtReg->reg);
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continue;
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}
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@ -139,6 +140,7 @@ void RegAllocBase::allocatePhysRegs() {
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assert(!VRM->hasPhys(SplitVirtReg->reg) && "Register already assigned");
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if (MRI->reg_nodbg_empty(SplitVirtReg->reg)) {
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DEBUG(dbgs() << "not queueing unused " << *SplitVirtReg << '\n');
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aboutToRemoveInterval(*SplitVirtReg);
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LIS->removeInterval(SplitVirtReg->reg);
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continue;
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}
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@ -96,6 +96,9 @@ protected:
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// Use this group name for NamedRegionTimer.
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static const char TimerGroupName[];
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/// Method called when the allocator is about to remove a LiveInterval.
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virtual void aboutToRemoveInterval(LiveInterval &LI) {}
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public:
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/// VerifyEnabled - True when -verify-regalloc is given.
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static bool VerifyEnabled;
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@ -296,6 +296,9 @@ class RAGreedy : public MachineFunctionPass,
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/// obtained from the TargetSubtargetInfo.
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bool EnableLocalReassign;
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/// Set of broken hints that may be reconciled later because of eviction.
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SmallSetVector<LiveInterval *, 8> SetOfBrokenHints;
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public:
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RAGreedy();
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@ -311,6 +314,7 @@ public:
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void enqueue(LiveInterval *LI) override;
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LiveInterval *dequeue() override;
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unsigned selectOrSplit(LiveInterval&, SmallVectorImpl<unsigned>&) override;
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void aboutToRemoveInterval(LiveInterval &) override;
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/// Perform register allocation.
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bool runOnMachineFunction(MachineFunction &mf) override;
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@ -378,6 +382,24 @@ private:
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SmallVirtRegSet &, unsigned);
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bool tryRecoloringCandidates(PQueue &, SmallVectorImpl<unsigned> &,
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SmallVirtRegSet &, unsigned);
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void tryHintRecoloring(LiveInterval &);
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void tryHintsRecoloring();
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/// Model the information carried by one end of a copy.
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struct HintInfo {
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/// The frequency of the copy.
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BlockFrequency Freq;
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/// The virtual register or physical register.
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unsigned Reg;
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/// Its currently assigned register.
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/// In case of a physical register Reg == PhysReg.
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unsigned PhysReg;
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HintInfo(BlockFrequency Freq, unsigned Reg, unsigned PhysReg)
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: Freq(Freq), Reg(Reg), PhysReg(PhysReg) {}
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};
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typedef SmallVector<HintInfo, 4> HintsInfo;
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BlockFrequency getBrokenHintFreq(const HintsInfo &, unsigned);
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void collectHintInfo(unsigned, HintsInfo &);
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};
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} // end anonymous namespace
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@ -453,7 +475,9 @@ void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
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bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) {
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if (VRM->hasPhys(VirtReg)) {
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Matrix->unassign(LIS->getInterval(VirtReg));
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LiveInterval &LI = LIS->getInterval(VirtReg);
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Matrix->unassign(LI);
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aboutToRemoveInterval(LI);
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return true;
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}
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// Unassigned virtreg is probably in the priority queue.
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@ -2213,6 +2237,11 @@ unsigned RAGreedy::tryAssignCSRFirstTime(LiveInterval &VirtReg,
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return PhysReg;
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}
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void RAGreedy::aboutToRemoveInterval(LiveInterval &LI) {
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// Do not keep invalid information around.
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SetOfBrokenHints.remove(&LI);
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}
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void RAGreedy::initializeCSRCost() {
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// We use the larger one out of the command-line option and the value report
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// by TRI.
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@ -2238,6 +2267,170 @@ void RAGreedy::initializeCSRCost() {
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CSRCost = CSRCost.getFrequency() * (ActualEntry / FixedEntry);
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}
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/// \brief Collect the hint info for \p Reg.
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/// The results are stored into \p Out.
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/// \p Out is not cleared before being populated.
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void RAGreedy::collectHintInfo(unsigned Reg, HintsInfo &Out) {
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for (const MachineInstr &Instr : MRI->reg_nodbg_instructions(Reg)) {
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if (!Instr.isFullCopy())
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continue;
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// Look for the other end of the copy.
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unsigned OtherReg = Instr.getOperand(0).getReg();
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if (OtherReg == Reg) {
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OtherReg = Instr.getOperand(1).getReg();
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if (OtherReg == Reg)
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continue;
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}
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// Get the current assignment.
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unsigned OtherPhysReg = TargetRegisterInfo::isPhysicalRegister(OtherReg)
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? OtherReg
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: VRM->getPhys(OtherReg);
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// Push the collected information.
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Out.push_back(HintInfo(MBFI->getBlockFreq(Instr.getParent()), OtherReg,
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OtherPhysReg));
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}
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}
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/// \brief Using the given \p List, compute the cost of the broken hints if
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/// \p PhysReg was used.
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/// \return The cost of \p List for \p PhysReg.
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BlockFrequency RAGreedy::getBrokenHintFreq(const HintsInfo &List,
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unsigned PhysReg) {
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BlockFrequency Cost = 0;
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for (const HintInfo &Info : List) {
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if (Info.PhysReg != PhysReg)
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Cost += Info.Freq;
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}
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return Cost;
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}
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/// \brief Using the register assigned to \p VirtReg, try to recolor
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/// all the live ranges that are copy-related with \p VirtReg.
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/// The recoloring is then propagated to all the live-ranges that have
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/// been recolored and so on, until no more copies can be coalesced or
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/// it is not profitable.
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/// For a given live range, profitability is determined by the sum of the
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/// frequencies of the non-identity copies it would introduce with the old
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/// and new register.
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void RAGreedy::tryHintRecoloring(LiveInterval &VirtReg) {
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// We have a broken hint, check if it is possible to fix it by
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// reusing PhysReg for the copy-related live-ranges. Indeed, we evicted
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// some register and PhysReg may be available for the other live-ranges.
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SmallSet<unsigned, 4> Visited;
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SmallVector<unsigned, 2> RecoloringCandidates;
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HintsInfo Info;
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unsigned Reg = VirtReg.reg;
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unsigned PhysReg = VRM->getPhys(Reg);
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// Start the recoloring algorithm from the input live-interval, then
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// it will propagate to the ones that are copy-related with it.
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Visited.insert(Reg);
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RecoloringCandidates.push_back(Reg);
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DEBUG(dbgs() << "Trying to reconcile hints for: " << PrintReg(Reg, TRI) << '('
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<< PrintReg(PhysReg, TRI) << ")\n");
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do {
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Reg = RecoloringCandidates.pop_back_val();
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// We cannot recolor physcal register.
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if (TargetRegisterInfo::isPhysicalRegister(Reg))
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continue;
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assert(VRM->hasPhys(Reg) && "We have unallocated variable!!");
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// Get the live interval mapped with this virtual register to be able
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// to check for the interference with the new color.
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LiveInterval &LI = LIS->getInterval(Reg);
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unsigned CurrPhys = VRM->getPhys(Reg);
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// Check that the new color matches the register class constraints and
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// that it is free for this live range.
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if (CurrPhys != PhysReg && (!MRI->getRegClass(Reg)->contains(PhysReg) ||
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Matrix->checkInterference(LI, PhysReg)))
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continue;
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DEBUG(dbgs() << PrintReg(Reg, TRI) << '(' << PrintReg(CurrPhys, TRI)
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<< ") is recolorable.\n");
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// Gather the hint info.
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Info.clear();
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collectHintInfo(Reg, Info);
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// Check if recoloring the live-range will increase the cost of the
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// non-identity copies.
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if (CurrPhys != PhysReg) {
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DEBUG(dbgs() << "Checking profitability:\n");
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BlockFrequency OldCopiesCost = getBrokenHintFreq(Info, CurrPhys);
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BlockFrequency NewCopiesCost = getBrokenHintFreq(Info, PhysReg);
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DEBUG(dbgs() << "Old Cost: " << OldCopiesCost.getFrequency()
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<< "\nNew Cost: " << NewCopiesCost.getFrequency() << '\n');
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if (OldCopiesCost < NewCopiesCost) {
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DEBUG(dbgs() << "=> Not profitable.\n");
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continue;
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}
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// At this point, the cost is either cheaper or equal. If it is
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// equal, we consider this is profitable because it may expose
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// more recoloring opportunities.
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DEBUG(dbgs() << "=> Profitable.\n");
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// Recolor the live-range.
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Matrix->unassign(LI);
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Matrix->assign(LI, PhysReg);
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}
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// Push all copy-related live-ranges to keep reconciling the broken
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// hints.
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for (const HintInfo &HI : Info) {
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if (Visited.insert(HI.Reg).second)
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RecoloringCandidates.push_back(HI.Reg);
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}
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} while (!RecoloringCandidates.empty());
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}
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/// \brief Try to recolor broken hints.
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/// Broken hints may be repaired by recoloring when an evicted variable
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/// freed up a register for a larger live-range.
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/// Consider the following example:
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/// BB1:
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/// a =
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/// b =
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/// BB2:
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/// ...
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/// = b
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/// = a
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/// Let us assume b gets split:
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/// BB1:
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/// a =
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/// b =
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/// BB2:
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/// c = b
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/// ...
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/// d = c
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/// = d
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/// = a
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/// Because of how the allocation work, b, c, and d may be assigned different
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/// colors. Now, if a gets evicted later:
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/// BB1:
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/// a =
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/// st a, SpillSlot
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/// b =
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/// BB2:
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/// c = b
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/// ...
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/// d = c
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/// = d
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/// e = ld SpillSlot
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/// = e
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/// This is likely that we can assign the same register for b, c, and d,
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/// getting rid of 2 copies.
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void RAGreedy::tryHintsRecoloring() {
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for (LiveInterval *LI : SetOfBrokenHints) {
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assert(TargetRegisterInfo::isVirtualRegister(LI->reg) &&
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"Recoloring is possible only for virtual registers");
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// Some dead defs may be around (e.g., because of debug uses).
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// Ignore those.
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if (!VRM->hasPhys(LI->reg))
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continue;
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tryHintRecoloring(*LI);
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}
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}
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unsigned RAGreedy::selectOrSplitImpl(LiveInterval &VirtReg,
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SmallVectorImpl<unsigned> &NewVRegs,
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SmallVirtRegSet &FixedRegisters,
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@ -2274,8 +2467,18 @@ unsigned RAGreedy::selectOrSplitImpl(LiveInterval &VirtReg,
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// queue. The RS_Split ranges already failed to do this, and they should not
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// get a second chance until they have been split.
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if (Stage != RS_Split)
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if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs, CostPerUseLimit))
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if (unsigned PhysReg =
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tryEvict(VirtReg, Order, NewVRegs, CostPerUseLimit)) {
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unsigned Hint = MRI->getSimpleHint(VirtReg.reg);
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// If VirtReg has a hint and that hint is broken record this
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// virtual register as a recoloring candidate for broken hint.
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// Indeed, since we evicted a variable in its neighborhood it is
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// likely we can at least partially recolor some of the
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// copy-related live-ranges.
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if (Hint && Hint != PhysReg)
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SetOfBrokenHints.insert(&VirtReg);
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return PhysReg;
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}
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assert(NewVRegs.empty() && "Cannot append to existing NewVRegs");
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@ -2355,8 +2558,10 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
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NextCascade = 1;
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IntfCache.init(MF, Matrix->getLiveUnions(), Indexes, LIS, TRI);
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GlobalCand.resize(32); // This will grow as needed.
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SetOfBrokenHints.clear();
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allocatePhysRegs();
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tryHintsRecoloring();
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releaseMemory();
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return true;
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}
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@ -0,0 +1,145 @@
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; RUN: llc < %s -o - -mtriple=x86_64-apple-macosx | FileCheck %s
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; Test case for the recoloring of broken hints.
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; This is tricky to have something reasonably small to kick this optimization since
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; it requires that spliting and spilling occur.
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; The bottom line is that this test case is fragile.
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; This was reduced from the make_list function from the llvm-testsuite:
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; SingleSource/Benchmarks/McGill/chomp.c
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target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-apple-macosx10.9.0"
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%struct._list = type { i32*, %struct._list* }
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@ncol = external global i32, align 4
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@nrow = external global i32, align 4
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declare noalias i32* @copy_data()
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declare noalias i8* @malloc(i64)
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declare i32 @get_value()
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declare i32 @in_wanted(i32* nocapture readonly)
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declare noalias i32* @make_data()
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; CHECK-LABEL: make_list:
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; Function prologue.
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; CHECK: pushq
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; CHECK: subq ${{[0-9]+}}, %rsp
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; Move the first argument (%data) into a temporary register.
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; It will not survive the call to malloc otherwise.
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; CHECK: movq %rdi, [[ARG1:%r[0-9a-z]+]]
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; CHECK: callq _malloc
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; Compute %data - 1 as used for load in land.rhs.i (via the variable %indvars.iv.next.i).
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; CHECK: addq $-4, [[ARG1]]
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; We use to produce a useless copy here and move %data in another temporary register.
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; CHECK-NOT: movq [[ARG1]]
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; End of the first basic block.
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; CHECK: .align
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; Now check that %data is used in an address computation.
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; CHECK: leaq ([[ARG1]]
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define %struct._list* @make_list(i32* nocapture readonly %data, i32* nocapture %value, i32* nocapture %all) {
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entry:
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%call = tail call i8* @malloc(i64 16)
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%next = getelementptr inbounds i8* %call, i64 8
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%tmp = bitcast i8* %next to %struct._list**
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%tmp2 = bitcast i8* %call to %struct._list*
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%.pre78 = load i32* @ncol, align 4
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br label %for.cond1.preheader
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for.cond1.preheader: ; preds = %for.inc32, %entry
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%tmp4 = phi i32 [ %.pre78, %entry ], [ 0, %for.inc32 ]
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%current.077 = phi %struct._list* [ %tmp2, %entry ], [ %current.1.lcssa, %for.inc32 ]
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%cmp270 = icmp eq i32 %tmp4, 0
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br i1 %cmp270, label %for.inc32, label %for.body3
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for.body3: ; preds = %if.end31, %for.cond1.preheader
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%current.173 = phi %struct._list* [ %current.2, %if.end31 ], [ %current.077, %for.cond1.preheader ]
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%row.172 = phi i32 [ %row.3, %if.end31 ], [ 0, %for.cond1.preheader ]
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%col.071 = phi i32 [ %inc, %if.end31 ], [ 0, %for.cond1.preheader ]
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%call4 = tail call i32* @make_data()
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%tmp5 = load i32* @ncol, align 4
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%tobool14.i = icmp eq i32 %tmp5, 0
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br i1 %tobool14.i, label %while.cond.i, label %while.body.lr.ph.i
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while.body.lr.ph.i: ; preds = %for.body3
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%tmp6 = sext i32 %tmp5 to i64
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br label %while.body.i
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while.body.i: ; preds = %while.body.i, %while.body.lr.ph.i
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%indvars.iv.i = phi i64 [ %tmp6, %while.body.lr.ph.i ], [ %indvars.iv.next.i, %while.body.i ]
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%indvars.iv.next.i = add nsw i64 %indvars.iv.i, -1
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%tmp9 = trunc i64 %indvars.iv.next.i to i32
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%tobool.i = icmp eq i32 %tmp9, 0
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br i1 %tobool.i, label %while.cond.i, label %while.body.i
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while.cond.i: ; preds = %land.rhs.i, %while.body.i, %for.body3
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%indvars.iv.i64 = phi i64 [ %indvars.iv.next.i65, %land.rhs.i ], [ 0, %for.body3 ], [ %tmp6, %while.body.i ]
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%indvars.iv.next.i65 = add nsw i64 %indvars.iv.i64, -1
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%tmp10 = trunc i64 %indvars.iv.i64 to i32
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%tobool.i66 = icmp eq i32 %tmp10, 0
|
||||
br i1 %tobool.i66, label %if.else, label %land.rhs.i
|
||||
|
||||
land.rhs.i: ; preds = %while.cond.i
|
||||
%arrayidx.i67 = getelementptr inbounds i32* %call4, i64 %indvars.iv.next.i65
|
||||
%tmp11 = load i32* %arrayidx.i67, align 4
|
||||
%arrayidx2.i68 = getelementptr inbounds i32* %data, i64 %indvars.iv.next.i65
|
||||
%tmp12 = load i32* %arrayidx2.i68, align 4
|
||||
%cmp.i69 = icmp eq i32 %tmp11, %tmp12
|
||||
br i1 %cmp.i69, label %while.cond.i, label %equal_data.exit
|
||||
|
||||
equal_data.exit: ; preds = %land.rhs.i
|
||||
%cmp3.i = icmp slt i32 %tmp10, 1
|
||||
br i1 %cmp3.i, label %if.else, label %if.then
|
||||
|
||||
if.then: ; preds = %equal_data.exit
|
||||
%next7 = getelementptr inbounds %struct._list* %current.173, i64 0, i32 1
|
||||
%tmp14 = load %struct._list** %next7, align 8
|
||||
%next12 = getelementptr inbounds %struct._list* %tmp14, i64 0, i32 1
|
||||
store %struct._list* null, %struct._list** %next12, align 8
|
||||
%tmp15 = load %struct._list** %next7, align 8
|
||||
%tmp16 = load i32* %value, align 4
|
||||
%cmp14 = icmp eq i32 %tmp16, 1
|
||||
%.tmp16 = select i1 %cmp14, i32 0, i32 %tmp16
|
||||
%tmp18 = load i32* %all, align 4
|
||||
%tmp19 = or i32 %tmp18, %.tmp16
|
||||
%tmp20 = icmp eq i32 %tmp19, 0
|
||||
br i1 %tmp20, label %if.then19, label %if.end31
|
||||
|
||||
if.then19: ; preds = %if.then
|
||||
%call21 = tail call i32 @in_wanted(i32* %call4)
|
||||
br label %if.end31
|
||||
|
||||
if.else: ; preds = %equal_data.exit, %while.cond.i
|
||||
%cmp26 = icmp eq i32 %col.071, 0
|
||||
%.row.172 = select i1 %cmp26, i32 0, i32 %row.172
|
||||
%sub30 = add nsw i32 %tmp5, -1
|
||||
br label %if.end31
|
||||
|
||||
if.end31: ; preds = %if.else, %if.then19, %if.then
|
||||
%col.1 = phi i32 [ %sub30, %if.else ], [ 0, %if.then ], [ 0, %if.then19 ]
|
||||
%row.3 = phi i32 [ %.row.172, %if.else ], [ %row.172, %if.then ], [ 0, %if.then19 ]
|
||||
%current.2 = phi %struct._list* [ %current.173, %if.else ], [ %tmp15, %if.then ], [ %tmp15, %if.then19 ]
|
||||
%inc = add nsw i32 %col.1, 1
|
||||
%tmp25 = load i32* @ncol, align 4
|
||||
%cmp2 = icmp eq i32 %inc, %tmp25
|
||||
br i1 %cmp2, label %for.cond1.for.inc32_crit_edge, label %for.body3
|
||||
|
||||
for.cond1.for.inc32_crit_edge: ; preds = %if.end31
|
||||
%.pre79 = load i32* @nrow, align 4
|
||||
br label %for.inc32
|
||||
|
||||
for.inc32: ; preds = %for.cond1.for.inc32_crit_edge, %for.cond1.preheader
|
||||
%tmp26 = phi i32 [ %.pre79, %for.cond1.for.inc32_crit_edge ], [ 0, %for.cond1.preheader ]
|
||||
%current.1.lcssa = phi %struct._list* [ %current.2, %for.cond1.for.inc32_crit_edge ], [ %current.077, %for.cond1.preheader ]
|
||||
%row.1.lcssa = phi i32 [ %row.3, %for.cond1.for.inc32_crit_edge ], [ 0, %for.cond1.preheader ]
|
||||
%inc33 = add nsw i32 %row.1.lcssa, 1
|
||||
%cmp = icmp eq i32 %inc33, %tmp26
|
||||
br i1 %cmp, label %for.end34, label %for.cond1.preheader
|
||||
|
||||
for.end34: ; preds = %for.inc32
|
||||
%.pre = load %struct._list** %tmp, align 8
|
||||
ret %struct._list* %.pre
|
||||
}
|
||||
Loading…
Reference in New Issue