From a76cd10fcda53160dd213157740b2efb31e73e8d Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sun, 1 Nov 2020 10:16:50 -0800 Subject: [PATCH] [RISCV] Use 'unsigned' instead of Register in getRegForInlineAsmConstraint. NFC The return value of this interface still uses an 'unsigned' on all targets. So we convert Register back to unsigned at the end. I'm hoping this will prevent the issue that caused the revert of D90322. --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index d2606f4e8b7c..b16743a688ad 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -2674,7 +2674,7 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, // official names. However, other frontends like `rustc` do not. This allows // users of these frontends to use the ABI names for registers in LLVM-style // register constraints. - Register XRegFromAlias = StringSwitch(Constraint.lower()) + unsigned XRegFromAlias = StringSwitch(Constraint.lower()) .Case("{zero}", RISCV::X0) .Case("{ra}", RISCV::X1) .Case("{sp}", RISCV::X2) @@ -2719,8 +2719,8 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, // The second case is the ABI name of the register, so that frontends can also // use the ABI names in register constraint lists. if (Subtarget.hasStdExtF() || Subtarget.hasStdExtD()) { - std::pair FReg = - StringSwitch>(Constraint.lower()) + std::pair FReg = + StringSwitch>(Constraint.lower()) .Cases("{f0}", "{ft0}", {RISCV::F0_F, RISCV::F0_D}) .Cases("{f1}", "{ft1}", {RISCV::F1_F, RISCV::F1_D}) .Cases("{f2}", "{ft2}", {RISCV::F2_F, RISCV::F2_D})