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[AMDGPU] Make more use of Subtarget reference in SIInstrInfo

This commit is contained in:
Jay Foad 2020-08-26 14:53:41 +01:00
parent 09af378f49
commit a75e67b3b4
1 changed files with 4 additions and 16 deletions
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20
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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@ -991,8 +991,6 @@ void SIInstrInfo::insertVectorSelect(MachineBasicBlock &MBB,
Register TrueReg, Register TrueReg,
Register FalseReg) const { Register FalseReg) const {
MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
MachineFunction *MF = MBB.getParent();
const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
const TargetRegisterClass *BoolXExecRC = const TargetRegisterClass *BoolXExecRC =
RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID); RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
assert(MRI.getRegClass(DstReg) == &AMDGPU::VGPR_32RegClass && assert(MRI.getRegClass(DstReg) == &AMDGPU::VGPR_32RegClass &&
@ -1496,7 +1494,6 @@ unsigned SIInstrInfo::calculateLDSSpillAddress(
unsigned FrameOffset, unsigned Size) const { unsigned FrameOffset, unsigned Size) const {
MachineFunction *MF = MBB.getParent(); MachineFunction *MF = MBB.getParent();
SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>(); SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
const DebugLoc &DL = MBB.findDebugLoc(MI); const DebugLoc &DL = MBB.findDebugLoc(MI);
unsigned WorkGroupSize = MFI->getMaxFlatWorkGroupSize(); unsigned WorkGroupSize = MFI->getMaxFlatWorkGroupSize();
unsigned WavefrontSize = ST.getWavefrontSize(); unsigned WavefrontSize = ST.getWavefrontSize();
@ -3312,9 +3309,6 @@ bool SIInstrInfo::isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
if (OpInfo.RegClass < 0) if (OpInfo.RegClass < 0)
return false; return false;
const MachineFunction *MF = MI.getParent()->getParent();
const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
if (MO.isImm() && isInlineConstant(MO, OpInfo)) { if (MO.isImm() && isInlineConstant(MO, OpInfo)) {
if (isMAI(MI) && ST.hasMFMAInlineLiteralBug() && if (isMAI(MI) && ST.hasMFMAInlineLiteralBug() &&
OpNo ==(unsigned)AMDGPU::getNamedOperandIdx(MI.getOpcode(), OpNo ==(unsigned)AMDGPU::getNamedOperandIdx(MI.getOpcode(),
@ -3849,7 +3843,6 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
} }
} }
} }
const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
// v_writelane_b32 is an exception from constant bus restriction: // v_writelane_b32 is an exception from constant bus restriction:
// vsrc0 can be sgpr, const or m0 and lane select sgpr, m0 or inline-const // vsrc0 can be sgpr, const or m0 and lane select sgpr, m0 or inline-const
if (ConstantBusCount > ST.getConstantBusLimit(Opcode) && if (ConstantBusCount > ST.getConstantBusLimit(Opcode) &&
@ -4017,7 +4010,7 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
} }
} }
if (isFLAT(MI) && !MF->getSubtarget<GCNSubtarget>().hasFlatInstOffsets()) { if (isFLAT(MI) && !ST.hasFlatInstOffsets()) {
const MachineOperand *Offset = getNamedOperand(MI, AMDGPU::OpName::offset); const MachineOperand *Offset = getNamedOperand(MI, AMDGPU::OpName::offset);
if (Offset->getImm() != 0) { if (Offset->getImm() != 0) {
ErrInfo = "subtarget does not support offsets in flat instructions"; ErrInfo = "subtarget does not support offsets in flat instructions";
@ -4236,11 +4229,9 @@ void SIInstrInfo::legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const {
MachineBasicBlock *MBB = MI.getParent(); MachineBasicBlock *MBB = MI.getParent();
MachineOperand &MO = MI.getOperand(OpIdx); MachineOperand &MO = MI.getOperand(OpIdx);
MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
const SIRegisterInfo *TRI =
static_cast<const SIRegisterInfo*>(MRI.getTargetRegisterInfo());
unsigned RCID = get(MI.getOpcode()).OpInfo[OpIdx].RegClass; unsigned RCID = get(MI.getOpcode()).OpInfo[OpIdx].RegClass;
const TargetRegisterClass *RC = RI.getRegClass(RCID); const TargetRegisterClass *RC = RI.getRegClass(RCID);
unsigned Size = TRI->getRegSizeInBits(*RC); unsigned Size = RI.getRegSizeInBits(*RC);
unsigned Opcode = (Size == 64) ? AMDGPU::V_MOV_B64_PSEUDO : AMDGPU::V_MOV_B32_e32; unsigned Opcode = (Size == 64) ? AMDGPU::V_MOV_B64_PSEUDO : AMDGPU::V_MOV_B32_e32;
if (MO.isReg()) if (MO.isReg())
Opcode = AMDGPU::COPY; Opcode = AMDGPU::COPY;
@ -4361,7 +4352,6 @@ bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
const MachineRegisterInfo &MRI = MF.getRegInfo(); const MachineRegisterInfo &MRI = MF.getRegInfo();
const MCInstrDesc &InstDesc = MI.getDesc(); const MCInstrDesc &InstDesc = MI.getDesc();
const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx]; const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
const TargetRegisterClass *DefinedRC = const TargetRegisterClass *DefinedRC =
OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr; OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
if (!MO) if (!MO)
@ -5181,8 +5171,7 @@ void SIInstrInfo::legalizeOperands(MachineInstr &MI,
} else if (!VAddr && ST.hasAddr64()) { } else if (!VAddr && ST.hasAddr64()) {
// This instructions is the _OFFSET variant, so we need to convert it to // This instructions is the _OFFSET variant, so we need to convert it to
// ADDR64. // ADDR64.
assert(MBB.getParent()->getSubtarget<GCNSubtarget>().getGeneration() assert(ST.getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS &&
< AMDGPUSubtarget::VOLCANIC_ISLANDS &&
"FIXME: Need to emit flat atomics here"); "FIXME: Need to emit flat atomics here");
unsigned RsrcPtr, NewSRsrc; unsigned RsrcPtr, NewSRsrc;
@ -6663,8 +6652,7 @@ unsigned SIInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
case TargetOpcode::INLINEASM_BR: { case TargetOpcode::INLINEASM_BR: {
const MachineFunction *MF = MI.getParent()->getParent(); const MachineFunction *MF = MI.getParent()->getParent();
const char *AsmStr = MI.getOperand(0).getSymbolName(); const char *AsmStr = MI.getOperand(0).getSymbolName();
return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo(), return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo(), &ST);
&MF->getSubtarget());
} }
default: default:
return DescSize; return DescSize;