forked from OSchip/llvm-project
[DAG] Prune store merge legal store check to stop invalid size. NFCI.
Do not consider store sizes large than the maximum legal store size. llvm-svn: 333763
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@ -13555,6 +13555,11 @@ bool DAGCombiner::MergeConsecutiveStores(StoreSDNode *St) {
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unsigned SizeInBits = (i + 1) * ElementSizeBytes * 8;
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EVT StoreTy = EVT::getIntegerVT(Context, SizeInBits);
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bool IsFast = false;
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// Break early when size is too large to be legal.
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if (StoreTy.getSizeInBits() > MaximumLegalStoreInBits)
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break;
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if (TLI.isTypeLegal(StoreTy) &&
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TLI.canMergeStoresTo(FirstStoreAS, StoreTy, DAG) &&
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TLI.allowsMemoryAccess(Context, DL, StoreTy, FirstStoreAS,
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@ -13658,6 +13663,11 @@ bool DAGCombiner::MergeConsecutiveStores(StoreSDNode *St) {
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EVT Ty =
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EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), Elts);
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bool IsFast;
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// Break early when size is too large to be legal.
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if (Ty.getSizeInBits() > MaximumLegalStoreInBits)
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break;
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if (TLI.isTypeLegal(Ty) &&
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TLI.canMergeStoresTo(FirstStoreAS, Ty, DAG) &&
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TLI.allowsMemoryAccess(Context, DL, Ty, FirstStoreAS,
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@ -13715,6 +13725,7 @@ bool DAGCombiner::MergeConsecutiveStores(StoreSDNode *St) {
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// Find acceptable loads. Loads need to have the same chain (token factor),
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// must not be zext, volatile, indexed, and they must be consecutive.
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BaseIndexOffset LdBasePtr;
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for (unsigned i = 0; i < NumConsecutiveStores; ++i) {
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StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
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SDValue Val = peekThroughBitcast(St->getValue());
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@ -13784,6 +13795,10 @@ bool DAGCombiner::MergeConsecutiveStores(StoreSDNode *St) {
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unsigned Elts = (i + 1) * NumMemElts;
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EVT StoreTy = EVT::getVectorVT(Context, MemVT.getScalarType(), Elts);
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// Break early when size is too large to be legal.
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if (StoreTy.getSizeInBits() > MaximumLegalStoreInBits)
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break;
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bool IsFastSt, IsFastLd;
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if (TLI.isTypeLegal(StoreTy) &&
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TLI.canMergeStoresTo(FirstStoreAS, StoreTy, DAG) &&
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