maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

AMDGPU: Move si_mask_branch register operand to be a use 

llvm-svn: 274818
This commit is contained in:
Matt Arsenault 2016-07-08 00:55:44 +00:00
parent d4a84b1ed2
commit a74374a86b
3 changed files with 8 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
View File

@ -113,7 +113,7 @@ void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
SmallVector<char, 16> BBStr;
raw_svector_ostream Str(BBStr);
const MachineBasicBlock *MBB = MI->getOperand(1).getMBB();
const MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
const MCSymbolRefExpr *Expr
= MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
Expr->print(Str, MAI);

2
llvm/lib/Target/AMDGPU/SIInstructions.td
View File

@ -1929,7 +1929,7 @@ let hasSideEffects = 1, isPseudo = 1, isCodeGenOnly = 1 in {
// Dummy terminator instruction to use after control flow instructions
// replaced with exec mask operations.
def SI_MASK_BRANCH : InstSI <
(outs SReg_64:$dst), (ins brtarget:$target)> {
(outs), (ins brtarget:$target, SReg_64:$dst)> {
let isBranch = 1;
let isTerminator = 1;
let isBarrier = 1;

10
llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
View File

@ -237,8 +237,9 @@ void SILowerControlFlow::If(MachineInstr &MI) {
Skip(MI, MI.getOperand(2));
// Insert a pseudo terminator to help keep the verifier happy.
BuildMI(MBB, &MI, DL, TII->get(AMDGPU::SI_MASK_BRANCH), Reg)
.addOperand(MI.getOperand(2));
BuildMI(MBB, &MI, DL, TII->get(AMDGPU::SI_MASK_BRANCH))
.addOperand(MI.getOperand(2))
.addReg(Reg);
MI.eraseFromParent();
}
@ -269,8 +270,9 @@ void SILowerControlFlow::Else(MachineInstr &MI, bool ExecModified) {
Skip(MI, MI.getOperand(2));
// Insert a pseudo terminator to help keep the verifier happy.
BuildMI(MBB, &MI, DL, TII->get(AMDGPU::SI_MASK_BRANCH), Dst)
.addOperand(MI.getOperand(2));
BuildMI(MBB, &MI, DL, TII->get(AMDGPU::SI_MASK_BRANCH))
.addOperand(MI.getOperand(2))
.addReg(Dst);
MI.eraseFromParent();
}