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Handle sse turning on mmx, but no -mmx not turning off SSE. 

Rationale :

// sse3
__m128d test_mm_addsub_pd(__m128d A, __m128d B) {
  return _mm_addsub_pd(A, B);
}

// mmx
void shift(__m64 a, __m64 b, int c) {
  _mm_slli_pi16(a, c);
  _mm_slli_pi32(a, c);
  _mm_slli_si64(a, c);
  _mm_srli_pi16(a, c);
  _mm_srli_pi32(a, c);
  _mm_srli_si64(a, c);
  _mm_srai_pi16(a, c);
  _mm_srai_pi32(a, c);
}

clang -msse3 -mno-mmx file.c -c

For this code we should be able to explicitly turn off MMX
without affecting the compilation of the SSE3 function and then
diagnose and error on compiling the MMX function.

This is a preparatory patch to the actual diagnosis code which is
coming in a future patch. This sets us up to have the correct information
where we need it and verifies that it's being emitted for the backend
to handle.

llvm-svn: 249733
This commit is contained in:
Eric Christopher 2015-10-08 20:10:18 +00:00
parent bbd746db9e
commit a7260af7e5
3 changed files with 39 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
clang/lib/Basic/Targets.cpp
View File

@ -2725,6 +2725,14 @@ bool X86TargetInfo::initFeatureMap(
FeaturesVec.end())
Features["prfchw"] = true;
// Additionally, if SSE is enabled and mmx is not explicitly disabled,
// then enable MMX.
I = Features.find("sse");
if (I != Features.end() && I->getValue() == true &&
std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") ==
FeaturesVec.end())
Features["mmx"] = true;
return true;
}
@ -3004,17 +3012,6 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
return false;
}
// Don't tell the backend if we're turning off mmx; it will end up disabling
// SSE, which we don't want.
// Additionally, if SSE is enabled and mmx is not explicitly disabled,
// then enable MMX.
std::vector<std::string>::iterator it;
it = std::find(Features.begin(), Features.end(), "-mmx");
if (it != Features.end())
Features.erase(it);
else if (SSELevel > NoSSE)
MMX3DNowLevel = std::max(MMX3DNowLevel, MMX);
SimdDefaultAlign =
hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
return true;

22
clang/test/CodeGen/attr-target-x86-mmx.c Normal file
View File

@ -0,0 +1,22 @@
// RUN: %clang_cc1 -triple i386-linux-gnu -emit-llvm %s -o - | FileCheck %s
// Picking a cpu that doesn't have mmx or sse by default so we can enable it later.
#define __MM_MALLOC_H
#include <x86intrin.h>
// Verify that when we turn on sse that we also turn on mmx.
void __attribute__((target("sse"))) shift(__m64 a, __m64 b, int c) {
_mm_slli_pi16(a, c);
_mm_slli_pi32(a, c);
_mm_slli_si64(a, c);
_mm_srli_pi16(a, c);
_mm_srli_pi32(a, c);
_mm_srli_si64(a, c);
_mm_srai_pi16(a, c);
_mm_srai_pi32(a, c);
}
// CHECK: "target-features"="+mmx,+sse"

14
clang/test/CodeGen/attr-target-x86.c
View File

@ -16,6 +16,8 @@ int bar(int a) { return baz(a) + foo(a); }
int __attribute__((target("avx, sse4.2, arch= ivybridge"))) qux(int a) { return 4; }
int __attribute__((target("no-aes, arch=ivybridge"))) qax(int a) { return 4; }
int __attribute__((target("no-mmx"))) qq(int a) { return 40; }
// Check that we emit the additional subtarget and cpu features for foo and not for baz or bar.
// CHECK: baz{{.*}} #0
// CHECK: foo{{.*}} #1
@ -28,8 +30,10 @@ int __attribute__((target("no-aes, arch=ivybridge"))) qax(int a) { return 4; }
// CHECK: bar{{.*}} #0
// CHECK: qux{{.*}} #1
// CHECK: qax{{.*}} #4
// CHECK: #0 = {{.*}}"target-cpu"="x86-64" "target-features"="+sse,+sse2"
// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" "target-features"="+aes,+avx,+cx16,+f16c,+fsgsbase,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3"
// CHECK: #2 = {{.*}}"target-cpu"="x86-64" "target-features"="+sse,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512pf,-avx512vl,-f16c,-fma,-fma4,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-xop"
// CHECK: #3 = {{.*}}"target-cpu"="x86-64" "target-features"="+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3"
// CHECK: #4 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cx16,+f16c,+fsgsbase,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,-aes"
// CHECK: qq{{.*}} #5
// CHECK: #0 = {{.*}}"target-cpu"="x86-64" "target-features"="+mmx,+sse,+sse2"
// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" "target-features"="+aes,+avx,+cx16,+f16c,+fsgsbase,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3"
// CHECK: #2 = {{.*}}"target-cpu"="x86-64" "target-features"="+mmx,+sse,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512pf,-avx512vl,-f16c,-fma,-fma4,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-xop"
// CHECK: #3 = {{.*}}"target-cpu"="x86-64" "target-features"="+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3"
// CHECK: #4 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cx16,+f16c,+fsgsbase,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,-aes"
// CHECK: #5 = {{.*}}"target-cpu"="x86-64" "target-features"="+sse,+sse2,-3dnow,-3dnowa,-mmx"