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[ARM] Remove unused lowerABS function. NFC 

This function was added in D49837, but no setOperationAction call
was added with it. The code is equivalent to what is done by the
default ExpandIntRes_ABS implementation when ADDCARRY is supported.
Test case added to verify this. There was some existing coverage
from Thumb2 MVE tests, but they started from vectors.
This commit is contained in:
Craig Topper 2022-02-20 22:35:30 -08:00
parent 47b1fa5fc4
commit a6fb1bb306
3 changed files with 14 additions and 37 deletions
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35
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -10514,9 +10514,6 @@ void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
return;
case ISD::INTRINSIC_WO_CHAIN:
return ReplaceLongIntrinsic(N, Results, DAG);
case ISD::ABS:
lowerABS(N, Results, DAG);
return ;
case ISD::LOAD:
LowerLOAD(N, Results, DAG);
break;
@ -20541,38 +20538,6 @@ SDValue ARMTargetLowering::LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
return IsStrict ? DAG.getMergeValues({Result, Chain}, Loc) : Result;
}
void ARMTargetLowering::lowerABS(SDNode *N, SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG) const {
assert(N->getValueType(0) == MVT::i64 && "Unexpected type (!= i64) on ABS.");
MVT HalfT = MVT::i32;
SDLoc dl(N);
SDValue Hi, Lo, Tmp;
if (!isOperationLegalOrCustom(ISD::ADDCARRY, HalfT) ||
!isOperationLegalOrCustom(ISD::UADDO, HalfT))
return ;
unsigned OpTypeBits = HalfT.getScalarSizeInBits();
SDVTList VTList = DAG.getVTList(HalfT, MVT::i1);
Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(0),
DAG.getConstant(0, dl, HalfT));
Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(0),
DAG.getConstant(1, dl, HalfT));
Tmp = DAG.getNode(ISD::SRA, dl, HalfT, Hi,
DAG.getConstant(OpTypeBits - 1, dl,
getShiftAmountTy(HalfT, DAG.getDataLayout())));
Lo = DAG.getNode(ISD::UADDO, dl, VTList, Tmp, Lo);
Hi = DAG.getNode(ISD::ADDCARRY, dl, VTList, Tmp, Hi,
SDValue(Lo.getNode(), 1));
Hi = DAG.getNode(ISD::XOR, dl, HalfT, Tmp, Hi);
Lo = DAG.getNode(ISD::XOR, dl, HalfT, Tmp, Lo);
Results.push_back(Lo);
Results.push_back(Hi);
}
bool
ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
// The ARM target isn't yet aware of offsets.

2
llvm/lib/Target/ARM/ARMISelLowering.h
View File

@ -845,8 +845,6 @@ class VectorType;
SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFSETCC(SDValue Op, SelectionDAG &DAG) const;
void lowerABS(SDNode *N, SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG) const;
void LowerLOAD(SDNode *N, SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG) const;

14
llvm/test/CodeGen/ARM/iabs.ll
View File

@ -32,3 +32,17 @@ entry:
%cond = select i1 %cmp, i32 %sub, i32 %sub1
ret i32 %cond
}
define i64 @test3(i64 %a) {
; CHECK-LABEL: test3:
; CHECK: @ %bb.0:
; CHECK-NEXT: adds r0, r0, r1, asr #31
; CHECK-NEXT: adc r2, r1, r1, asr #31
; CHECK-NEXT: eor r0, r0, r1, asr #31
; CHECK-NEXT: eor r1, r2, r1, asr #31
; CHECK-NEXT: bx lr
%tmp1neg = sub i64 0, %a
%b = icmp sgt i64 %a, -1
%abs = select i1 %b, i64 %a, i64 %tmp1neg
ret i64 %abs
}