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[AArch64][SVE] Asm: Support for CPY SIMD/FP and GPR instructions. 

Predicated splat/copy of SIMD/FP register or general purpose
register to SVE vector, along with MOV-aliases.

llvm-svn: 334842
This commit is contained in:
Sander de Smalen 2018-06-15 16:39:46 +00:00
parent 7e535bc4bf
commit a6edca72ba
6 changed files with 447 additions and 0 deletions
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4
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
View File

@ -53,6 +53,10 @@ let Predicates = [HasSVE] in {
defm DUP_ZR : sve_int_perm_dup_r<"dup">;
defm DUP_ZZI : sve_int_perm_dup_i<"dup">;
// Splat scalar register (predicated)
defm CPY_ZPmR : sve_int_perm_cpy_r<"cpy">;
defm CPY_ZPmV : sve_int_perm_cpy_v<"cpy">;
// continuous load with reg+immediate
defm LD1B_IMM : sve_mem_cld_si<0b0000, "ld1b", Z_b, ZPR8>;
defm LD1B_H_IMM : sve_mem_cld_si<0b0001, "ld1b", Z_h, ZPR16>;

75
llvm/lib/Target/AArch64/SVEInstrFormats.td
View File

@ -1453,6 +1453,81 @@ multiclass sve_int_perm_bin_perm_pp<bits<3> opc, string asm> {
def _D : sve_int_perm_bin_perm_pp<opc, 0b11, asm, PPR64>;
}
//===----------------------------------------------------------------------===//
// SVE Permute Vector - Predicated Group
//===----------------------------------------------------------------------===//
class sve_int_perm_cpy_r<bits<2> sz8_64, string asm, ZPRRegOp zprty,
RegisterClass srcRegType>
: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, srcRegType:$Rn),
asm, "\t$Zd, $Pg/m, $Rn",
"",
[]>, Sched<[]> {
bits<3> Pg;
bits<5> Rn;
bits<5> Zd;
let Inst{31-24} = 0b00000101;
let Inst{23-22} = sz8_64;
let Inst{21-13} = 0b101000101;
let Inst{12-10} = Pg;
let Inst{9-5} = Rn;
let Inst{4-0} = Zd;
let Constraints = "$Zd = $_Zd";
}
multiclass sve_int_perm_cpy_r<string asm> {
def _B : sve_int_perm_cpy_r<0b00, asm, ZPR8, GPR32sp>;
def _H : sve_int_perm_cpy_r<0b01, asm, ZPR16, GPR32sp>;
def _S : sve_int_perm_cpy_r<0b10, asm, ZPR32, GPR32sp>;
def _D : sve_int_perm_cpy_r<0b11, asm, ZPR64, GPR64sp>;
def : InstAlias<"mov $Zd, $Pg/m, $Rn",
(!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn), 1>;
def : InstAlias<"mov $Zd, $Pg/m, $Rn",
(!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn), 1>;
def : InstAlias<"mov $Zd, $Pg/m, $Rn",
(!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn), 1>;
def : InstAlias<"mov $Zd, $Pg/m, $Rn",
(!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPR3bAny:$Pg, GPR64sp:$Rn), 1>;
}
class sve_int_perm_cpy_v<bits<2> sz8_64, string asm, ZPRRegOp zprty,
RegisterClass srcRegtype>
: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, srcRegtype:$Vn),
asm, "\t$Zd, $Pg/m, $Vn",
"",
[]>, Sched<[]> {
bits<3> Pg;
bits<5> Vn;
bits<5> Zd;
let Inst{31-24} = 0b00000101;
let Inst{23-22} = sz8_64;
let Inst{21-13} = 0b100000100;
let Inst{12-10} = Pg;
let Inst{9-5} = Vn;
let Inst{4-0} = Zd;
let Constraints = "$Zd = $_Zd";
}
multiclass sve_int_perm_cpy_v<string asm> {
def _B : sve_int_perm_cpy_v<0b00, asm, ZPR8, FPR8>;
def _H : sve_int_perm_cpy_v<0b01, asm, ZPR16, FPR16>;
def _S : sve_int_perm_cpy_v<0b10, asm, ZPR32, FPR32>;
def _D : sve_int_perm_cpy_v<0b11, asm, ZPR64, FPR64>;
def : InstAlias<"mov $Zd, $Pg/m, $Vn",
(!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPR3bAny:$Pg, FPR8:$Vn), 1>;
def : InstAlias<"mov $Zd, $Pg/m, $Vn",
(!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPR3bAny:$Pg, FPR16:$Vn), 1>;
def : InstAlias<"mov $Zd, $Pg/m, $Vn",
(!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPR3bAny:$Pg, FPR32:$Vn), 1>;
def : InstAlias<"mov $Zd, $Pg/m, $Vn",
(!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPR3bAny:$Pg, FPR64:$Vn), 1>;
}
//===----------------------------------------------------------------------===//
// SVE Memory - Contiguous Load Group
//===----------------------------------------------------------------------===//

84
llvm/test/MC/AArch64/SVE/cpy-diagnostics.s
View File

@ -1,5 +1,89 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Invalid scalar operand for result element width.
cpy z0.b, p0/m, x0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: cpy z0.b, p0/m, x0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cpy z0.h, p0/m, x0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: cpy z0.h, p0/m, x0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cpy z0.s, p0/m, x0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: cpy z0.s, p0/m, x0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cpy z0.d, p0/m, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: cpy z0.d, p0/m, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cpy z0.b, p0/m, h0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: cpy z0.b, p0/m, h0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cpy z0.b, p0/m, s0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: cpy z0.b, p0/m, s0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cpy z0.b, p0/m, d0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: cpy z0.b, p0/m, d0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cpy z0.h, p0/m, b0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: cpy z0.h, p0/m, b0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cpy z0.h, p0/m, s0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: cpy z0.h, p0/m, s0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cpy z0.h, p0/m, d0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: cpy z0.h, p0/m, d0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cpy z0.s, p0/m, b0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: cpy z0.s, p0/m, b0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cpy z0.s, p0/m, h0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: cpy z0.s, p0/m, h0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cpy z0.s, p0/m, d0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: cpy z0.s, p0/m, d0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cpy z0.d, p0/m, b0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: cpy z0.d, p0/m, b0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cpy z0.d, p0/m, h0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: cpy z0.d, p0/m, h0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
cpy z0.d, p0/m, s0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: cpy z0.d, p0/m, s0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid immediates

96
llvm/test/MC/AArch64/SVE/cpy.s
View File

@ -7,6 +7,102 @@
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
cpy z0.b, p0/m, w0
// CHECK-INST: mov z0.b, p0/m, w0
// CHECK-ENCODING: [0x00,0xa0,0x28,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 28 05 <unknown>
cpy z0.h, p0/m, w0
// CHECK-INST: mov z0.h, p0/m, w0
// CHECK-ENCODING: [0x00,0xa0,0x68,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 68 05 <unknown>
cpy z0.s, p0/m, w0
// CHECK-INST: mov z0.s, p0/m, w0
// CHECK-ENCODING: [0x00,0xa0,0xa8,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 a8 05 <unknown>
cpy z0.d, p0/m, x0
// CHECK-INST: mov z0.d, p0/m, x0
// CHECK-ENCODING: [0x00,0xa0,0xe8,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 e8 05 <unknown>
cpy z31.b, p7/m, wsp
// CHECK-INST: mov z31.b, p7/m, wsp
// CHECK-ENCODING: [0xff,0xbf,0x28,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 28 05 <unknown>
cpy z31.h, p7/m, wsp
// CHECK-INST: mov z31.h, p7/m, wsp
// CHECK-ENCODING: [0xff,0xbf,0x68,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 68 05 <unknown>
cpy z31.s, p7/m, wsp
// CHECK-INST: mov z31.s, p7/m, wsp
// CHECK-ENCODING: [0xff,0xbf,0xa8,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf a8 05 <unknown>
cpy z31.d, p7/m, sp
// CHECK-INST: mov z31.d, p7/m, sp
// CHECK-ENCODING: [0xff,0xbf,0xe8,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf e8 05 <unknown>
cpy z0.b, p0/m, b0
// CHECK-INST: mov z0.b, p0/m, b0
// CHECK-ENCODING: [0x00,0x80,0x20,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 20 05 <unknown>
cpy z31.b, p7/m, b31
// CHECK-INST: mov z31.b, p7/m, b31
// CHECK-ENCODING: [0xff,0x9f,0x20,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 9f 20 05 <unknown>
cpy z0.h, p0/m, h0
// CHECK-INST: mov z0.h, p0/m, h0
// CHECK-ENCODING: [0x00,0x80,0x60,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 60 05 <unknown>
cpy z31.h, p7/m, h31
// CHECK-INST: mov z31.h, p7/m, h31
// CHECK-ENCODING: [0xff,0x9f,0x60,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 9f 60 05 <unknown>
cpy z0.s, p0/m, s0
// CHECK-INST: mov z0.s, p0/m, s0
// CHECK-ENCODING: [0x00,0x80,0xa0,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 a0 05 <unknown>
cpy z31.s, p7/m, s31
// CHECK-INST: mov z31.s, p7/m, s31
// CHECK-ENCODING: [0xff,0x9f,0xa0,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 9f a0 05 <unknown>
cpy z0.d, p0/m, d0
// CHECK-INST: mov z0.d, p0/m, d0
// CHECK-ENCODING: [0x00,0x80,0xe0,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 e0 05 <unknown>
cpy z31.d, p7/m, d31
// CHECK-INST: mov z31.d, p7/m, d31
// CHECK-ENCODING: [0xff,0x9f,0xe0,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 9f e0 05 <unknown>
cpy z5.b, p0/z, #-128
// CHECK-INST: mov z5.b, p0/z, #-128
// CHECK-ENCODING: [0x05,0x10,0x10,0x05]

88
llvm/test/MC/AArch64/SVE/mov-diagnostics.s
View File

@ -37,6 +37,94 @@ mov z0.s, z1.s
// CHECK-NEXT: mov z0.s, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid scalar operand for result element width.
mov z0.d, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: mov z0.d, w0
// CHECK-NOT: [[@LINE-3]]:{{[0-9]+}}:
mov z0.b, p0/m, x0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: mov z0.b, p0/m, x0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mov z0.h, p0/m, x0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: mov z0.h, p0/m, x0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mov z0.s, p0/m, x0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: mov z0.s, p0/m, x0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mov z0.d, p0/m, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: mov z0.d, p0/m, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mov z0.b, p0/m, h0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: mov z0.b, p0/m, h0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mov z0.b, p0/m, s0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: mov z0.b, p0/m, s0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mov z0.b, p0/m, d0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: mov z0.b, p0/m, d0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mov z0.h, p0/m, b0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: mov z0.h, p0/m, b0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mov z0.h, p0/m, s0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: mov z0.h, p0/m, s0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mov z0.h, p0/m, d0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: mov z0.h, p0/m, d0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mov z0.s, p0/m, b0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: mov z0.s, p0/m, b0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mov z0.s, p0/m, h0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: mov z0.s, p0/m, h0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mov z0.s, p0/m, d0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: mov z0.s, p0/m, d0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mov z0.d, p0/m, b0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: mov z0.d, p0/m, b0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mov z0.d, p0/m, h0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: mov z0.d, p0/m, h0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
mov z0.d, p0/m, s0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: mov z0.d, p0/m, s0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid immediates

100
llvm/test/MC/AArch64/SVE/mov.s
View File

@ -500,3 +500,103 @@ mov z5.q, z17.q[3]
// CHECK-ENCODING: [0x25,0x22,0xf0,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 25 22 f0 05 <unknown>
// --------------------------------------------------------------------------//
// Tests for predicated copy of SIMD/FP registers.
mov z0.b, p0/m, w0
// CHECK-INST: mov z0.b, p0/m, w0
// CHECK-ENCODING: [0x00,0xa0,0x28,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 28 05 <unknown>
mov z0.h, p0/m, w0
// CHECK-INST: mov z0.h, p0/m, w0
// CHECK-ENCODING: [0x00,0xa0,0x68,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 68 05 <unknown>
mov z0.s, p0/m, w0
// CHECK-INST: mov z0.s, p0/m, w0
// CHECK-ENCODING: [0x00,0xa0,0xa8,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 a8 05 <unknown>
mov z0.d, p0/m, x0
// CHECK-INST: mov z0.d, p0/m, x0
// CHECK-ENCODING: [0x00,0xa0,0xe8,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 a0 e8 05 <unknown>
mov z31.b, p7/m, wsp
// CHECK-INST: mov z31.b, p7/m, wsp
// CHECK-ENCODING: [0xff,0xbf,0x28,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 28 05 <unknown>
mov z31.h, p7/m, wsp
// CHECK-INST: mov z31.h, p7/m, wsp
// CHECK-ENCODING: [0xff,0xbf,0x68,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 68 05 <unknown>
mov z31.s, p7/m, wsp
// CHECK-INST: mov z31.s, p7/m, wsp
// CHECK-ENCODING: [0xff,0xbf,0xa8,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf a8 05 <unknown>
mov z31.d, p7/m, sp
// CHECK-INST: mov z31.d, p7/m, sp
// CHECK-ENCODING: [0xff,0xbf,0xe8,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf e8 05 <unknown>
mov z0.b, p0/m, b0
// CHECK-INST: mov z0.b, p0/m, b0
// CHECK-ENCODING: [0x00,0x80,0x20,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 20 05 <unknown>
mov z31.b, p7/m, b31
// CHECK-INST: mov z31.b, p7/m, b31
// CHECK-ENCODING: [0xff,0x9f,0x20,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 9f 20 05 <unknown>
mov z0.h, p0/m, h0
// CHECK-INST: mov z0.h, p0/m, h0
// CHECK-ENCODING: [0x00,0x80,0x60,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 60 05 <unknown>
mov z31.h, p7/m, h31
// CHECK-INST: mov z31.h, p7/m, h31
// CHECK-ENCODING: [0xff,0x9f,0x60,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 9f 60 05 <unknown>
mov z0.s, p0/m, s0
// CHECK-INST: mov z0.s, p0/m, s0
// CHECK-ENCODING: [0x00,0x80,0xa0,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 a0 05 <unknown>
mov z31.s, p7/m, s31
// CHECK-INST: mov z31.s, p7/m, s31
// CHECK-ENCODING: [0xff,0x9f,0xa0,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 9f a0 05 <unknown>
mov z0.d, p0/m, d0
// CHECK-INST: mov z0.d, p0/m, d0
// CHECK-ENCODING: [0x00,0x80,0xe0,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 e0 05 <unknown>
mov z31.d, p7/m, d31
// CHECK-INST: mov z31.d, p7/m, d31
// CHECK-ENCODING: [0xff,0x9f,0xe0,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 9f e0 05 <unknown>