From a6cda12179b881731106ee86ee9600e45f6db5d6 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Fri, 6 May 2016 12:57:26 +0000 Subject: [PATCH] [mips][fastisel] Conditional moves do not have implicit operands. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19862 llvm-svn: 268730 --- llvm/lib/Target/Mips/MipsFastISel.cpp | 9 ++++----- llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll | 4 ++-- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/llvm/lib/Target/Mips/MipsFastISel.cpp b/llvm/lib/Target/Mips/MipsFastISel.cpp index d215ed7977dc..f8535290d3b2 100644 --- a/llvm/lib/Target/Mips/MipsFastISel.cpp +++ b/llvm/lib/Target/Mips/MipsFastISel.cpp @@ -692,11 +692,10 @@ bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) { emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1); emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg( Mips::FCC0, RegState::ImplicitDefine); - MachineInstrBuilder MI = emitInst(CondMovOpc, ResultReg) - .addReg(RegWithOne) - .addReg(Mips::FCC0) - .addReg(RegWithZero, RegState::Implicit); - MI->tieOperands(0, 3); + emitInst(CondMovOpc, ResultReg) + .addReg(RegWithOne) + .addReg(Mips::FCC0) + .addReg(RegWithZero); break; } } diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll b/llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll index e346acfeff13..d661a281ea1d 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ -; RUN: < %s | FileCheck %s +; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ -; RUN: < %s | FileCheck %s +; RUN: -verify-machineinstrs < %s | FileCheck %s @f1 = common global float 0.000000e+00, align 4 @f2 = common global float 0.000000e+00, align 4