forked from OSchip/llvm-project
[X86] Add PTEST tests showing failure to extract allsign cases
As discussed on PR42035, we can often use MOVMSK to avoid a cmpgt/ashr by just analysing the extracted signbits.
This commit is contained in:
Simon Pilgrim
parent
c8b7c73c57
commit
a6c4cd3bcb
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@ -1,5 +1,6 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX2
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;
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; testz(~X,Y) -> testc(X,Y)
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@ -297,6 +298,102 @@ start:
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ret i1 %6
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}
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;
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; TODO: testz(ashr(X,bw-1),-1) -> movmsk(X)
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;
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define i32 @ptestz_v2i64_signbits(<2 x i64> %c, i32 %a, i32 %b) {
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; CHECK-LABEL: ptestz_v2i64_signbits:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; CHECK-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0
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; CHECK-NEXT: vptest %xmm0, %xmm0
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; CHECK-NEXT: cmovnel %esi, %eax
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; CHECK-NEXT: retq
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%t1 = ashr <2 x i64> %c, <i64 63, i64 63>
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%t2 = call i32 @llvm.x86.sse41.ptestz(<2 x i64> %t1, <2 x i64> <i64 -1, i64 -1>)
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%t3 = icmp ne i32 %t2, 0
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%t4 = select i1 %t3, i32 %a, i32 %b
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ret i32 %t4
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}
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define i32 @ptestz_v8i32_signbits(<8 x i32> %c, i32 %a, i32 %b) {
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; AVX1-LABEL: ptestz_v8i32_signbits:
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; AVX1: # %bb.0:
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; AVX1-NEXT: movl %edi, %eax
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; AVX1-NEXT: vpsrad $31, %xmm0, %xmm1
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
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; AVX1-NEXT: vpsrad $31, %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: vptest %ymm0, %ymm0
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; AVX1-NEXT: cmovnel %esi, %eax
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; AVX1-NEXT: vzeroupper
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: ptestz_v8i32_signbits:
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; AVX2: # %bb.0:
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; AVX2-NEXT: movl %edi, %eax
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; AVX2-NEXT: vpsrad $31, %ymm0, %ymm0
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; AVX2-NEXT: vptest %ymm0, %ymm0
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; AVX2-NEXT: cmovnel %esi, %eax
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; AVX2-NEXT: vzeroupper
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; AVX2-NEXT: retq
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%t1 = ashr <8 x i32> %c, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
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%t2 = bitcast <8 x i32> %t1 to <4 x i64>
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%t3 = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %t2, <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>)
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%t4 = icmp ne i32 %t3, 0
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%t5 = select i1 %t4, i32 %a, i32 %b
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ret i32 %t5
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}
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define i32 @ptestz_v8i16_signbits(<8 x i16> %c, i32 %a, i32 %b) {
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; CHECK-LABEL: ptestz_v8i16_signbits:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: vpsraw $15, %xmm0, %xmm0
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; CHECK-NEXT: vptest %xmm0, %xmm0
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; CHECK-NEXT: cmovnel %esi, %eax
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; CHECK-NEXT: retq
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%t1 = ashr <8 x i16> %c, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
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%t2 = bitcast <8 x i16> %t1 to <2 x i64>
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%t3 = call i32 @llvm.x86.sse41.ptestz(<2 x i64> %t2, <2 x i64> <i64 -1, i64 -1>)
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%t4 = icmp ne i32 %t3, 0
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%t5 = select i1 %t4, i32 %a, i32 %b
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ret i32 %t5
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}
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define i32 @ptestz_v32i8_signbits(<32 x i8> %c, i32 %a, i32 %b) {
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; AVX1-LABEL: ptestz_v32i8_signbits:
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; AVX1: # %bb.0:
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; AVX1-NEXT: movl %edi, %eax
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX1-NEXT: vpcmpgtb %xmm1, %xmm2, %xmm1
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; AVX1-NEXT: vpcmpgtb %xmm0, %xmm2, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: vptest %ymm0, %ymm0
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; AVX1-NEXT: cmovnel %esi, %eax
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; AVX1-NEXT: vzeroupper
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: ptestz_v32i8_signbits:
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; AVX2: # %bb.0:
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; AVX2-NEXT: movl %edi, %eax
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; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; AVX2-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm0
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; AVX2-NEXT: vptest %ymm0, %ymm0
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; AVX2-NEXT: cmovnel %esi, %eax
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; AVX2-NEXT: vzeroupper
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; AVX2-NEXT: retq
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%t1 = ashr <32 x i8> %c, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
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%t2 = bitcast <32 x i8> %t1 to <4 x i64>
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%t3 = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %t2, <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>)
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%t4 = icmp ne i32 %t3, 0
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%t5 = select i1 %t4, i32 %a, i32 %b
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ret i32 %t5
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}
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declare i32 @llvm.x86.sse41.ptestz(<2 x i64>, <2 x i64>) nounwind readnone
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declare i32 @llvm.x86.sse41.ptestc(<2 x i64>, <2 x i64>) nounwind readnone
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declare i32 @llvm.x86.sse41.ptestnzc(<2 x i64>, <2 x i64>) nounwind readnone
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