forked from OSchip/llvm-project
[AArch64] Add more addv tests
Differential Revision: https://reviews.llvm.org/D89365
This commit is contained in:
Vinay Madhusudan
parent
2c5f3d54c5
commit
a6ad5930d5
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@ -1,39 +1,57 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-eabi -aarch64-neon-syntax=generic | FileCheck %s
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; Function Attrs: nounwind readnone
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declare i64 @llvm.vector.reduce.add.v2i64(<2 x i64>)
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declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
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declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16>)
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declare i16 @llvm.vector.reduce.add.v4i16(<4 x i16>)
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declare i8 @llvm.vector.reduce.add.v8i8(<8 x i8>)
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declare i8 @llvm.vector.reduce.add.v16i8(<16 x i8>)
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define i8 @add_B(<16 x i8>* %arr) {
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; CHECK-LABEL: add_B
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; CHECK: addv {{b[0-9]+}}, {{v[0-9]+}}.16b
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; CHECK-LABEL: add_B:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: addv b0, v0.16b
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%bin.rdx = load <16 x i8>, <16 x i8>* %arr
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%r = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %bin.rdx)
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ret i8 %r
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}
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define i16 @add_H(<8 x i16>* %arr) {
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; CHECK-LABEL: add_H
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; CHECK: addv {{h[0-9]+}}, {{v[0-9]+}}.8h
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; CHECK-LABEL: add_H:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: addv h0, v0.8h
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%bin.rdx = load <8 x i16>, <8 x i16>* %arr
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%r = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %bin.rdx)
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ret i16 %r
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}
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define i32 @add_S( <4 x i32>* %arr) {
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; CHECK-LABEL: add_S
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; CHECK: addv {{s[0-9]+}}, {{v[0-9]+}}.4s
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; CHECK-LABEL: add_S:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: addv s0, v0.4s
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%bin.rdx = load <4 x i32>, <4 x i32>* %arr
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%r = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %bin.rdx)
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ret i32 %r
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}
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define i64 @add_D(<2 x i64>* %arr) {
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; CHECK-LABEL: add_D
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; CHECK-NOT: addv
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; CHECK: addp {{d[0-9]+}}, {{v[0-9]+}}.2d
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; CHECK-LABEL: add_D:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: addp d0, v0.2d
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; CHECK-NEXT: fmov x0, d0
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; CHECK-NEXT: ret
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%bin.rdx = load <2 x i64>, <2 x i64>* %arr
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%r = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %bin.rdx)
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ret i64 %r
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@ -42,8 +60,16 @@ define i64 @add_D(<2 x i64>* %arr) {
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declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)
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define i32 @oversized_ADDV_256(i8* noalias nocapture readonly %arg1, i8* noalias nocapture readonly %arg2) {
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; CHECK-LABEL: oversized_ADDV_256
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; CHECK: addv {{s[0-9]+}}, {{v[0-9]+}}.4s
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; CHECK-LABEL: oversized_ADDV_256:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: ldr d1, [x1]
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; CHECK-NEXT: uabdl v0.8h, v0.8b, v1.8b
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; CHECK-NEXT: ushll v1.4s, v0.4h, #0
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; CHECK-NEXT: uaddw2 v0.4s, v1.4s, v0.8h
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; CHECK-NEXT: addv s0, v0.4s
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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entry:
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%0 = bitcast i8* %arg1 to <8 x i8>*
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%1 = load <8 x i8>, <8 x i8>* %0, align 1
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@ -62,9 +88,81 @@ entry:
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declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)
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define i32 @oversized_ADDV_512(<16 x i32>* %arr) {
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; CHECK-LABEL: oversized_ADDV_512
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; CHECK: addv {{s[0-9]+}}, {{v[0-9]+}}.4s
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; CHECK-LABEL: oversized_ADDV_512:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0, #32]
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; CHECK-NEXT: ldp q3, q2, [x0]
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; CHECK-NEXT: add v1.4s, v2.4s, v1.4s
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; CHECK-NEXT: add v0.4s, v3.4s, v0.4s
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; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: addv s0, v0.4s
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%bin.rdx = load <16 x i32>, <16 x i32>* %arr
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%r = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %bin.rdx)
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ret i32 %r
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}
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define i8 @addv_combine_i8(<8 x i8> %a1, <8 x i8> %a2) {
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; CHECK-LABEL: addv_combine_i8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: addv b0, v0.8b
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; CHECK-NEXT: addv b1, v1.8b
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: fmov w9, s1
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; CHECK-NEXT: add w0, w8, w9
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; CHECK-NEXT: ret
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entry:
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%rdx.1 = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> %a1)
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%rdx.2 = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> %a2)
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%r = add i8 %rdx.1, %rdx.2
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ret i8 %r
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}
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define i16 @addv_combine_i16(<4 x i16> %a1, <4 x i16> %a2) {
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; CHECK-LABEL: addv_combine_i16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: addv h0, v0.4h
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; CHECK-NEXT: addv h1, v1.4h
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: fmov w9, s1
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; CHECK-NEXT: add w0, w8, w9
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; CHECK-NEXT: ret
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entry:
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%rdx.1 = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> %a1)
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%rdx.2 = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> %a2)
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%r = add i16 %rdx.1, %rdx.2
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ret i16 %r
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}
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define i32 @addv_combine_i32(<4 x i32> %a1, <4 x i32> %a2) {
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; CHECK-LABEL: addv_combine_i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: addv s0, v0.4s
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; CHECK-NEXT: addv s1, v1.4s
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: fmov w9, s1
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; CHECK-NEXT: add w0, w8, w9
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; CHECK-NEXT: ret
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entry:
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%rdx.1 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %a1)
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%rdx.2 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %a2)
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%r = add i32 %rdx.1, %rdx.2
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ret i32 %r
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}
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define i64 @addv_combine_i64(<2 x i64> %a1, <2 x i64> %a2) {
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; CHECK-LABEL: addv_combine_i64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: addp d0, v0.2d
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; CHECK-NEXT: addp d1, v1.2d
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; CHECK-NEXT: fmov x8, d0
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; CHECK-NEXT: fmov x9, d1
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; CHECK-NEXT: add x0, x8, x9
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; CHECK-NEXT: ret
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entry:
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%rdx.1 = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %a1)
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%rdx.2 = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %a2)
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%r = add i64 %rdx.1, %rdx.2
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ret i64 %r
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}
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