forked from OSchip/llvm-project
Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's
return ValueType can depend its operands' ValueType. This is a cosmetic change, no functionality impacted. llvm-svn: 48145
This commit is contained in:
parent
afa02ed5fb
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a6729e8666
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@ -109,9 +109,8 @@ public:
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/// srl/add/sra.
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bool isPow2DivCheap() const { return Pow2DivIsCheap; }
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/// getSetCCResultTy - Return the ValueType of the result of setcc operations.
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///
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MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; }
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/// getSetCCResultType - Return the ValueType of the result of setcc operations.
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virtual MVT::ValueType getSetCCResultType(const SDOperand &) const;
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/// getSetCCResultContents - For targets without boolean registers, this flag
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/// returns information about the contents of the high-bits in the setcc
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@ -707,10 +706,6 @@ protected:
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/// amounts. This type defaults to the pointer type.
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void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; }
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/// setSetCCResultType - Describe the type that shoudl be used as the result
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/// of a setcc operation. This defaults to the pointer type.
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void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; }
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/// setSetCCResultContents - Specify how the target extends the result of a
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/// setcc operation in a register.
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void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; }
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@ -1259,10 +1254,6 @@ private:
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/// it.
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bool Pow2DivIsCheap;
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/// SetCCResultTy - The type that SetCC operations use. This defaults to the
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/// PointerTy.
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MVT::ValueType SetCCResultTy;
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/// SetCCResultContents - Information about the contents of the high-bits in
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/// the result of a setcc comparison operation.
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SetCCResultValue SetCCResultContents;
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@ -2605,7 +2605,7 @@ SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
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return N2;
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// Determine if the condition we're dealing with is constant
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SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
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SDOperand SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false);
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if (SCC.Val) AddToWorkList(SCC.Val);
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if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
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@ -5077,7 +5077,7 @@ SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
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ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
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// Determine if the condition we're dealing with is constant
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SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
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SDOperand SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false);
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if (SCC.Val) AddToWorkList(SCC.Val);
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ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
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@ -5157,7 +5157,7 @@ SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
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SDOperand Temp, SCC;
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// cast from setcc result type to select result type
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if (AfterLegalize) {
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SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
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SCC = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC);
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if (N2.getValueType() < SCC.getValueType())
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Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
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else
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@ -5182,8 +5182,8 @@ SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
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// otherwise, go ahead with the folds.
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if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
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MVT::ValueType XType = N0.getValueType();
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if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
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SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
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if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(N0))) {
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SDOperand Res = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC);
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if (Res.getValueType() != VT)
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Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
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return Res;
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@ -3186,7 +3186,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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MVT::ValueType IVT =
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Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
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SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
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SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
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SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit),
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SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
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// Get the absolute value of the result.
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SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
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@ -3522,7 +3522,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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break;
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case ISD::CTTZ:
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//if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
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Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
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Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
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DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
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ISD::SETEQ);
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Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
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@ -3574,7 +3574,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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// Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
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MVT::ValueType VT = Node->getValueType(0);
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Tmp2 = DAG.getConstantFP(0.0, VT);
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Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
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Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
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ISD::SETUGT);
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Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
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Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
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break;
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@ -3780,7 +3781,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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APInt x = APInt::getSignBit(MVT::getSizeInBits(NVT));
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(void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
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Tmp2 = DAG.getConstantFP(apf, VT);
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Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
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Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)),
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Node->getOperand(0), Tmp2, ISD::SETLT);
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True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
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False = DAG.getNode(ISD::FP_TO_SINT, NVT,
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@ -4124,9 +4125,12 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
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break;
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case ISD::SETCC:
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assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
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Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
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Node->getOperand(1), Node->getOperand(2));
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assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0)))
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&& "SetCC type is not legal??");
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Result = DAG.getNode(ISD::SETCC,
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TLI.getSetCCResultType(Node->getOperand(0)),
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Node->getOperand(0), Node->getOperand(1),
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Node->getOperand(2));
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break;
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case ISD::TRUNCATE:
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@ -4484,7 +4488,7 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
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break;
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case ISD::CTTZ:
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// if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
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Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
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Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
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DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
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ISD::SETEQ);
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Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
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@ -4748,11 +4752,12 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
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Tmp2 = DAG.getConstant(0, MVT::i32);
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CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
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if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
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Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
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Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
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CC);
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LHS = ExpandLibCall(TLI.getLibcallName(LC2),
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DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
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false /*sign irrelevant*/, Dummy);
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Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
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Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
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DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
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Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
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Tmp2 = SDOperand();
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@ -4773,11 +4778,11 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
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// BNE crN, L:
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// FCMP crN, lo1, lo2
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// The following can be improved, but not that much.
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Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
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Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode);
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Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETEQ);
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Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
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Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
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Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE);
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Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode);
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Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETNE);
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Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
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Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
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Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
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Tmp2 = SDOperand();
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@ -4835,14 +4840,15 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
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// NOTE: on targets without efficient SELECT of bools, we can always use
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// this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
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TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
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Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
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false, DagCombineInfo);
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Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo,
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LowCC, false, DagCombineInfo);
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if (!Tmp1.Val)
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Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
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Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
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Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
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Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
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CCCode, false, DagCombineInfo);
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if (!Tmp2.Val)
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Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi,CC);
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Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi,
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RHSHi,CC);
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ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
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ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
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Tmp1 = Tmp2;
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Tmp2 = SDOperand();
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} else {
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Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
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Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
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ISD::SETEQ, false, DagCombineInfo);
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if (!Result.Val)
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Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
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Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
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ISD::SETEQ);
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Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
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Result, Tmp1, Tmp2));
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Tmp1 = Result;
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@ -5336,7 +5343,7 @@ ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
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SDOperand SignedConv = ExpandIntToFP(true, DestTy,
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DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi));
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SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
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SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
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DAG.getConstant(0, Hi.getValueType()),
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ISD::SETLT);
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SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
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@ -5489,7 +5496,7 @@ SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
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assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
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SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
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SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
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SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0,
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DAG.getConstant(0, Op0.getValueType()),
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ISD::SETLT);
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SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
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@ -5895,7 +5902,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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ExpandOp(Node->getOperand(0), Lo, Hi);
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SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
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SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
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SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
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SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC,
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ISD::SETNE);
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SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
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LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
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@ -5910,7 +5917,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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ExpandOp(Node->getOperand(0), Lo, Hi);
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SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
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SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
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SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
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SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC,
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ISD::SETNE);
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SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
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HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
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@ -632,7 +632,7 @@ void DAGTypeLegalizer::ExpandResult_CTLZ(SDNode *N,
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GetExpandedOp(N->getOperand(0), Lo, Hi);
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MVT::ValueType NVT = Lo.getValueType();
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SDOperand HiNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
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SDOperand HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
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DAG.getConstant(0, NVT), ISD::SETNE);
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SDOperand LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo);
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@ -660,7 +660,7 @@ void DAGTypeLegalizer::ExpandResult_CTTZ(SDNode *N,
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GetExpandedOp(N->getOperand(0), Lo, Hi);
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MVT::ValueType NVT = Lo.getValueType();
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SDOperand LoNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), Lo,
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SDOperand LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo,
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DAG.getConstant(0, NVT), ISD::SETNE);
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SDOperand LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
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@ -1031,7 +1031,7 @@ SDOperand DAGTypeLegalizer::ExpandOperand_UINT_TO_FP(SDOperand Source,
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SDOperand Lo, Hi;
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GetExpandedOp(Source, Lo, Hi);
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SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
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SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
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DAG.getConstant(0, Hi.getValueType()),
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ISD::SETLT);
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SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
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@ -1113,11 +1113,11 @@ void DAGTypeLegalizer::ExpandSetCCOperands(SDOperand &NewLHS, SDOperand &NewRHS,
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// FCMP crN, lo1, lo2
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// The following can be improved, but not that much.
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SDOperand Tmp1, Tmp2, Tmp3;
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Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
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Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode);
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Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETEQ);
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Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
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Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
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Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE);
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Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode);
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Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETNE);
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Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
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Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
|
||||
NewLHS = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
|
||||
NewRHS = SDOperand(); // LHS is the result, not a compare.
|
||||
|
@ -1174,14 +1174,14 @@ void DAGTypeLegalizer::ExpandSetCCOperands(SDOperand &NewLHS, SDOperand &NewRHS,
|
|||
// this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
|
||||
TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
|
||||
SDOperand Tmp1, Tmp2;
|
||||
Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
|
||||
Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC,
|
||||
false, DagCombineInfo);
|
||||
if (!Tmp1.Val)
|
||||
Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
|
||||
Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
|
||||
Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
|
||||
Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
|
||||
CCCode, false, DagCombineInfo);
|
||||
if (!Tmp2.Val)
|
||||
Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi,
|
||||
Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
|
||||
DAG.getCondCode(CCCode));
|
||||
|
||||
ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
|
||||
|
@ -1201,10 +1201,11 @@ void DAGTypeLegalizer::ExpandSetCCOperands(SDOperand &NewLHS, SDOperand &NewRHS,
|
|||
return;
|
||||
}
|
||||
|
||||
NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
|
||||
NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
|
||||
ISD::SETEQ, false, DagCombineInfo);
|
||||
if (!NewLHS.Val)
|
||||
NewLHS = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
|
||||
NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
|
||||
ISD::SETEQ);
|
||||
NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
|
||||
NewLHS, Tmp1, Tmp2);
|
||||
NewRHS = SDOperand();
|
||||
|
|
|
@ -186,9 +186,10 @@ SDOperand DAGTypeLegalizer::PromoteResult_FP_TO_XINT(SDNode *N) {
|
|||
}
|
||||
|
||||
SDOperand DAGTypeLegalizer::PromoteResult_SETCC(SDNode *N) {
|
||||
assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
|
||||
return DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), N->getOperand(0),
|
||||
N->getOperand(1), N->getOperand(2));
|
||||
assert(isTypeLegal(TLI.getSetCCResultType(N->getOperand(0)))
|
||||
&& "SetCC type is not legal??");
|
||||
return DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(N->getOperand(0)),
|
||||
N->getOperand(0), N->getOperand(1), N->getOperand(2));
|
||||
}
|
||||
|
||||
SDOperand DAGTypeLegalizer::PromoteResult_LOAD(LoadSDNode *N) {
|
||||
|
|
|
@ -1440,7 +1440,7 @@ void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
|
|||
// Emit the range check for the jump table, and branch to the default
|
||||
// block for the switch statement if the value being switched on exceeds
|
||||
// the largest case in the switch.
|
||||
SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
|
||||
SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
|
||||
DAG.getConstant(JTH.Last-JTH.First,VT),
|
||||
ISD::SETUGT);
|
||||
|
||||
|
@ -1473,7 +1473,7 @@ void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B)
|
|||
DAG.getConstant(B.First, VT));
|
||||
|
||||
// Check range
|
||||
SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
|
||||
SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
|
||||
DAG.getConstant(B.Range, VT),
|
||||
ISD::SETUGT);
|
||||
|
||||
|
@ -1526,7 +1526,7 @@ void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
|
|||
SwitchVal,
|
||||
DAG.getConstant(B.Mask,
|
||||
TLI.getPointerTy()));
|
||||
SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp,
|
||||
SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp,
|
||||
DAG.getConstant(0, TLI.getPointerTy()),
|
||||
ISD::SETNE);
|
||||
SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
|
||||
|
|
|
@ -191,7 +191,7 @@ TargetLowering::TargetLowering(TargetMachine &tm)
|
|||
|
||||
IsLittleEndian = TD->isLittleEndian();
|
||||
UsesGlobalOffsetTable = false;
|
||||
ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD->getIntPtrType());
|
||||
ShiftAmountTy = PointerTy = getValueType(TD->getIntPtrType());
|
||||
ShiftAmtHandling = Undefined;
|
||||
memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
|
||||
memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
|
||||
|
@ -372,6 +372,13 @@ const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
|
|||
return NULL;
|
||||
}
|
||||
|
||||
|
||||
MVT::ValueType
|
||||
TargetLowering::getSetCCResultType(const SDOperand &) const {
|
||||
return getValueType(TD->getIntPtrType());
|
||||
}
|
||||
|
||||
|
||||
/// getVectorTypeBreakdown - Vector types are broken down into some number of
|
||||
/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
|
||||
/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
|
||||
|
|
|
@ -40,7 +40,6 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
|
|||
// Set up the TargetLowering object.
|
||||
//I am having problems with shr n ubyte 1
|
||||
setShiftAmountType(MVT::i64);
|
||||
setSetCCResultType(MVT::i64);
|
||||
setSetCCResultContents(ZeroOrOneSetCCResult);
|
||||
|
||||
setUsesGlobalOffsetTable(true);
|
||||
|
@ -151,6 +150,11 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
|
|||
computeRegisterProperties();
|
||||
}
|
||||
|
||||
MVT::ValueType
|
||||
AlphaTargetLowering::getSetCCResultType(const SDOperand &) const {
|
||||
return MVT::i64;
|
||||
}
|
||||
|
||||
const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
|
||||
switch (Opcode) {
|
||||
default: return 0;
|
||||
|
|
|
@ -66,6 +66,9 @@ namespace llvm {
|
|||
public:
|
||||
explicit AlphaTargetLowering(TargetMachine &TM);
|
||||
|
||||
/// getSetCCResultType - Get the SETCC result ValueType
|
||||
virtual MVT::ValueType getSetCCResultType(const SDOperand &) const;
|
||||
|
||||
/// LowerOperation - Provide custom lowering hooks for some operations.
|
||||
///
|
||||
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
|
||||
|
|
|
@ -102,6 +102,9 @@ namespace llvm {
|
|||
/// getTargetNodeName() - This method returns the name of a target specific
|
||||
/// DAG node.
|
||||
virtual const char *getTargetNodeName(unsigned Opcode) const;
|
||||
|
||||
/// getSetCCResultType - Return the ValueType for ISD::SETCC
|
||||
MVT::ValueType getSetCCResultType(const SDOperand &) const;
|
||||
|
||||
/// LowerOperation - Provide custom lowering hooks for some operations.
|
||||
///
|
||||
|
|
|
@ -57,7 +57,6 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
|
|||
// br.ret insn
|
||||
setOperationAction(ISD::RET, MVT::Other, Custom);
|
||||
|
||||
setSetCCResultType(MVT::i1);
|
||||
setShiftAmountType(MVT::i64);
|
||||
|
||||
setOperationAction(ISD::FREM , MVT::f32 , Expand);
|
||||
|
@ -137,6 +136,10 @@ const char *IA64TargetLowering::getTargetNodeName(unsigned Opcode) const {
|
|||
}
|
||||
}
|
||||
|
||||
MVT::ValueType
|
||||
IA64TargetLowering::getSetCCResultType(const SDOperand &) const {
|
||||
return MVT::i1;
|
||||
}
|
||||
|
||||
std::vector<SDOperand>
|
||||
IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
|
||||
|
|
|
@ -47,6 +47,7 @@ namespace llvm {
|
|||
unsigned VirtGPR; // this is public so it can be accessed in the selector
|
||||
// for ISD::RET. add an accessor instead? FIXME
|
||||
const char *getTargetNodeName(unsigned Opcode) const;
|
||||
MVT::ValueType getSetCCResultType(const SDOperand &) const;
|
||||
|
||||
/// LowerArguments - This hook must be implemented to indicate how we should
|
||||
/// lower the arguments for the specified function, into the specified DAG.
|
||||
|
|
|
@ -52,7 +52,6 @@ MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
|
|||
{
|
||||
// Mips does not have i1 type, so use i32 for
|
||||
// setcc operations results (slt, sgt, ...).
|
||||
setSetCCResultType(MVT::i32);
|
||||
setSetCCResultContents(ZeroOrOneSetCCResult);
|
||||
|
||||
// JumpTable targets must use GOT when using PIC_
|
||||
|
@ -112,6 +111,12 @@ MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
|
|||
}
|
||||
|
||||
|
||||
MVT::ValueType
|
||||
MipsTargetLowering::getSetCCResultType(const SDOperand &) const {
|
||||
return MVT::i32;
|
||||
}
|
||||
|
||||
|
||||
SDOperand MipsTargetLowering::
|
||||
LowerOperation(SDOperand Op, SelectionDAG &DAG)
|
||||
{
|
||||
|
|
|
@ -62,6 +62,9 @@ namespace llvm {
|
|||
// DAG node.
|
||||
virtual const char *getTargetNodeName(unsigned Opcode) const;
|
||||
|
||||
/// getSetCCResultType - get the ISD::SETCC result ValueType
|
||||
MVT::ValueType getSetCCResultType(const SDOperand &) const;
|
||||
|
||||
private:
|
||||
// Lower Operand helpers
|
||||
SDOperand LowerCCCArguments(SDOperand Op, SelectionDAG &DAG);
|
||||
|
|
|
@ -324,7 +324,6 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
|
|||
setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
|
||||
}
|
||||
|
||||
setSetCCResultType(MVT::i32);
|
||||
setShiftAmountType(MVT::i32);
|
||||
setSetCCResultContents(ZeroOrOneSetCCResult);
|
||||
|
||||
|
@ -407,6 +406,13 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
|
|||
}
|
||||
}
|
||||
|
||||
|
||||
MVT::ValueType
|
||||
PPCTargetLowering::getSetCCResultType(const SDOperand &) const {
|
||||
return MVT::i32;
|
||||
}
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Node matching predicates, for use by the tblgen matching code.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
|
@ -213,6 +213,9 @@ namespace llvm {
|
|||
/// DAG node.
|
||||
virtual const char *getTargetNodeName(unsigned Opcode) const;
|
||||
|
||||
/// getSetCCResultType - Return the ISD::SETCC ValueType
|
||||
virtual MVT::ValueType getSetCCResultType(const SDOperand &) const;
|
||||
|
||||
/// getPreIndexedAddressParts - returns true by value, base pointer and
|
||||
/// offset pointer and addressing mode by reference if the node's address
|
||||
/// can be legally represented as pre-indexed load / store address.
|
||||
|
|
|
@ -57,7 +57,6 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
|
|||
|
||||
// X86 is weird, it always uses i8 for shift amounts and setcc results.
|
||||
setShiftAmountType(MVT::i8);
|
||||
setSetCCResultType(MVT::i8);
|
||||
setSetCCResultContents(ZeroOrOneSetCCResult);
|
||||
setSchedulingPreference(SchedulingForRegPressure);
|
||||
setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
|
||||
|
@ -728,6 +727,13 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
|
|||
setPrefLoopAlignment(16);
|
||||
}
|
||||
|
||||
|
||||
MVT::ValueType
|
||||
X86TargetLowering::getSetCCResultType(const SDOperand &) const {
|
||||
return MVT::i8;
|
||||
}
|
||||
|
||||
|
||||
/// getMaxByValAlign - Helper for getByValTypeAlignment to determine
|
||||
/// the desired ByVal argument alignment.
|
||||
static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
|
||||
|
|
|
@ -375,6 +375,9 @@ namespace llvm {
|
|||
/// DAG node.
|
||||
virtual const char *getTargetNodeName(unsigned Opcode) const;
|
||||
|
||||
/// getSetCCResultType - Return the ISD::SETCC ValueType
|
||||
virtual MVT::ValueType getSetCCResultType(const SDOperand &) const;
|
||||
|
||||
/// computeMaskedBitsForTargetNode - Determine which of the bits specified
|
||||
/// in Mask are known to be either zero or one and return them in the
|
||||
/// KnownZero/KnownOne bitsets.
|
||||
|
|
Loading…
Reference in New Issue