maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

Add missing implementation to the materialization of VFP misc. instructions (vmrs, vmsr and vmov (immediate)) 

llvm-svn: 104588
This commit is contained in:
Zonr Chang 2010-05-25 10:23:52 +00:00
parent 2da5aa1b60
commit a6714e8a43
1 changed files with 43 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

43
llvm/lib/Target/ARM/ARMCodeEmitter.cpp
View File

@ -1465,12 +1465,55 @@ ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
}
void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
unsigned Opcode = MI.getDesc().Opcode;
// Part of binary is determined by TableGn.
unsigned Binary = getBinaryCodeForInstr(MI);
// Set the conditional execution predicate
Binary |= II->getPredicate(&MI) << ARMII::CondShift;
switch(Opcode) {
default:
llvm_unreachable("ARMCodeEmitter::emitMiscInstruction");
case ARM::FMSTAT:
// No further encoding needed.
break;
case ARM::VMRS:
case ARM::VMSR: {
const MachineOperand &MO0 = MI.getOperand(0);
// Encode Rt.
Binary |= ARMRegisterInfo::getRegisterNumbering(MO0.getReg())
<< ARMII::RegRdShift;
break;
}
case ARM::FCONSTD:
case ARM::FCONSTS: {
// Encode Dd / Sd.
Binary |= encodeVFPRd(MI, 0);
// Encode imm., Table A7-18 VFP modified immediate constants
const MachineOperand &MO1 = MI.getOperand(1);
unsigned Imm = static_cast<unsigned>(MO1.getFPImm()->getValueAPF()
.bitcastToAPInt().getHiBits(32).getLimitedValue());
unsigned ModifiedImm;
if(Opcode == ARM::FCONSTS)
ModifiedImm = (Imm & 0x80000000) >> 24 | // a
(Imm & 0x03F80000) >> 19; // bcdefgh
else // Opcode == ARM::FCONSTD
ModifiedImm = (Imm & 0x80000000) >> 24 | // a
(Imm & 0x007F0000) >> 16; // bcdefgh
// Insts{19-16} = abcd, Insts{3-0} = efgh
Binary |= ((ModifiedImm & 0xF0) >> 4) << 16;
Binary |= (ModifiedImm & 0xF);
break;
}
}
emitWordLE(Binary);
}