[LLDB] Update AArch64 Dwarf and EH frame register numbers

This patch updates ARM64_ehframe_Registers.h and ARM64_DWARF_Registers.h
with latest register numbers in line with AArch64 SVE support.

For refernce take a look at "DWARF for the ARM® 64-bit Architecture (AArch64)
with SVE support" manual from Arm.
Version used: abi_sve_aadwarf_100985_0000_00_en.pdf
This commit is contained in:
Muhammad Omair Javaid 2020-07-08 01:22:35 +05:00
parent 50f24331fd
commit a65da5f592
2 changed files with 121 additions and 7 deletions

View File

@ -51,7 +51,31 @@ enum {
sp = x31,
pc = 32,
cpsr = 33,
// 34-63 reserved
// 34-45 reserved
// 64-bit SVE Vector granule pseudo register
vg = 46,
// VG ́8-bit SVE first fault register
ffr = 47,
// VG x ́8-bit SVE predicate registers
p0 = 48,
p1,
p2,
p3,
p4,
p5,
p6,
p7,
p8,
p9,
p10,
p11,
p12,
p13,
p14,
p15,
// V0-V31 (128 bit vector registers)
v0 = 64,
@ -85,9 +109,41 @@ enum {
v28,
v29,
v30,
v31
v31,
// 96-127 reserved
// VG ́64-bit SVE vector registers
z0 = 96,
z1,
z2,
z3,
z4,
z5,
z6,
z7,
z8,
z9,
z10,
z11,
z12,
z13,
z14,
z15,
z16,
z17,
z18,
z19,
z20,
z21,
z22,
z23,
z24,
z25,
z26,
z27,
z28,
z29,
z30,
z31
};
} // namespace arm64_dwarf

View File

@ -49,10 +49,34 @@ enum {
lr, // aka x30
sp, // aka x31 aka wzr
pc, // value is 32
cpsr
};
cpsr,
// 34-45 reserved
enum {
// 64-bit SVE Vector granule pseudo register
vg = 46,
// VG ́8-bit SVE first fault register
ffr = 47,
// VG x ́8-bit SVE predicate registers
p0 = 48,
p1,
p2,
p3,
p4,
p5,
p6,
p7,
p8,
p9,
p10,
p11,
p12,
p13,
p14,
p15,
// V0-V31 (128 bit vector registers)
v0 = 64,
v1,
v2,
@ -84,7 +108,41 @@ enum {
v28,
v29,
v30,
v31 // 95
v31,
// VG ́64-bit SVE vector registers
z0 = 96,
z1,
z2,
z3,
z4,
z5,
z6,
z7,
z8,
z9,
z10,
z11,
z12,
z13,
z14,
z15,
z16,
z17,
z18,
z19,
z20,
z21,
z22,
z23,
z24,
z25,
z26,
z27,
z28,
z29,
z30,
z31
};
}