[mips][microMIPS] Implement SW and SWE instructions

Differential Revision: http://reviews.llvm.org/D10869

llvm-svn: 245293
This commit is contained in:
Zoran Jovanovic 2015-08-18 12:53:08 +00:00
parent 4eb82578ea
commit a6593ff613
7 changed files with 105 additions and 0 deletions

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@ -951,6 +951,10 @@ public:
template <unsigned Bits> bool isMemWithSimmOffset() const {
return isMem() && isConstantMemOff() && isInt<Bits>(getConstantMemOff());
}
template <unsigned Bits> bool isMemWithSimmOffsetGPR() const {
return isMem() && isConstantMemOff() && isInt<Bits>(getConstantMemOff())
&& getMemBase()->isGPRAsmReg();
}
bool isMemWithGRPMM16Base() const {
return isMem() && getMemBase()->isMM16AsmReg();
}

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@ -284,6 +284,11 @@ static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
unsigned Insn,
uint64_t Address,
@ -1304,6 +1309,24 @@ static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
return MCDisassembler::Success;
}
static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
int Offset = SignExtend32<9>(Insn & 0x1ff);
unsigned Reg = fieldFromInstruction(Insn, 21, 5);
unsigned Base = fieldFromInstruction(Insn, 16, 5);
Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
Inst.addOperand(MCOperand::createReg(Reg));
Inst.addOperand(MCOperand::createReg(Base));
Inst.addOperand(MCOperand::createImm(Offset));
return MCDisassembler::Success;
}
static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
unsigned Insn,
uint64_t Address,

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@ -287,3 +287,33 @@ class SHIFT_MMR6_ENC<string instr_asm, bits<10> funct, bit rotate> : MMR6Arch<in
let Inst{10} = rotate;
let Inst{9-0} = funct;
}
class SW32_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {
bits<5> rt;
bits<21> addr;
bits<32> Inst;
let Inst{31-26} = op;
let Inst{25-21} = rt;
let Inst{20-16} = addr{20-16};
let Inst{15-0} = addr{15-0};
}
class POOL32C_SWE_FM_MMR6<string instr_asm, bits<6> op, bits<4> fmt,
bits<3> funct> : MMR6Arch<instr_asm> {
bits<5> rt;
bits<21> addr;
bits<5> base = addr{20-16};
bits<9> offset = addr{8-0};
bits<32> Inst;
let Inst{31-26} = op;
let Inst{25-21} = rt;
let Inst{20-16} = base;
let Inst{15-12} = fmt;
let Inst{11-9} = funct;
let Inst{8-0} = offset;
}

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@ -66,6 +66,8 @@ class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>;
class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0x3e>;
class SWE_MMR6_ENC : POOL32C_SWE_FM_MMR6<"swe", 0x18, 0xa, 0x7>;
class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
@ -108,6 +110,26 @@ class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm,
list<Register> Defs = [RA];
}
//===----------------------------------------------------------------------===//
//
// Operand Definitions
//
//===----------------------------------------------------------------------===//
def MipsMemSimm9GPRAsmOperand : AsmOperandClass {
let Name = "MemOffsetSimm9GPR";
let SuperClasses = [MipsMemAsmOperand];
let RenderMethod = "addMemOperands";
let ParserMethod = "parseMemOperand";
let PredicateMethod = "isMemWithSimmOffsetGPR<9>";
}
def mem_simm9gpr : mem_generic {
let MIOperandInfo = (ops ptr_rc, simm9);
let EncoderMethod = "getMemEncoding";
let ParserMatchClass = MipsMemSimm9GPRAsmOperand;
}
//===----------------------------------------------------------------------===//
//
// Instruction Descriptions
@ -277,6 +299,18 @@ class ORI_MMR6_DESC : ArithLogicI<"ori", simm16, GPR32Opnd>;
class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd>;
class XORI_MMR6_DESC : ArithLogicI<"xori", simm16, GPR32Opnd>;
class SWE_MMR6_DESC_BASE<string opstr, DAGOperand RO, DAGOperand MO,
SDPatternOperator OpNode = null_frag,
InstrItinClass Itin = NoItinerary,
ComplexPattern Addr = addr> :
InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
[(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
let DecoderMethod = "DecodeMem";
let mayStore = 1;
}
class SW_MMR6_DESC : Store<"sw", GPR32Opnd>;
class SWE_MMR6_DESC : SWE_MMR6_DESC_BASE<"swe", GPR32Opnd, mem_simm9gpr>;
//===----------------------------------------------------------------------===//
//
// Instruction Definitions
@ -348,6 +382,12 @@ def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
let DecoderMethod = "DecodeMemMMImm16" in {
def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6;
}
let DecoderMethod = "DecodeMemMMImm9" in {
def SWE_MMR6 : StdMMR6Rel, SWE_MMR6_DESC, SWE_MMR6_ENC, ISA_MICROMIPS32R6;
}
}
//===----------------------------------------------------------------------===//

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@ -112,3 +112,6 @@
0x00 0x64 0x3b 0x3c # CHECK: seh $3, $4
0xf8,0xa6,0x00,0x04 # CHECK: sw $5, 4($6)
0x60,0xa4,0xae,0x08 # CHECK: swe $5, 8($4)

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@ -4,3 +4,6 @@
break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
break 1023, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
ei $32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swe $33, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swe $5, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swe $5, 512($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

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@ -58,4 +58,6 @@
subu $3, $4, $5 # CHECK: subu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xd0]
xor $3, $4, $5 # CHECK: xor $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x10]
xori $3, $4, 1234 # CHECK: xori $3, $4, 1234 # encoding: [0x70,0x64,0x04,0xd2]
sw $5, 4($6) # CHECK: sw $5, 4($6) # encoding: [0xf8,0xa6,0x00,0x04]
swe $5, 8($4) # CHECK: swe $5, 8($4) # encoding: [0x60,0xa4,0xae,0x08]