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[AArch64][SVE] Allow explicit size specifier for predicate operand 

... for the vector forms of `{SQ,UQ,}{INC,DEC}P` instructions. Also continue
supporting the exsting behaviour of not requiring an explicit size
specifier. The preferred disasembly is *with* the specifier.

This is implemented by redefining intruction forms to require vector predicates
with explicit size and adding aliases, which allow a predicate with no size.

Differential Revision: https://reviews.llvm.org/D65145

llvm-svn: 367019
This commit is contained in:
Momchil Velikov 2019-07-25 13:56:04 +00:00
parent a85af76c72
commit a655f476b0
7 changed files with 152 additions and 37 deletions
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23
llvm/lib/Target/AArch64/SVEInstrFormats.td
View File

@ -403,12 +403,12 @@ multiclass sve_int_count_r_x64<bits<5> opc, string asm> {
}
class sve_int_count_v<bits<2> sz8_64, bits<5> opc, string asm,
ZPRRegOp zprty>
: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, PPRAny:$Pg),
asm, "\t$Zdn, $Pg",
ZPRRegOp zprty, PPRRegOp pprty>
: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, pprty:$Pm),
asm, "\t$Zdn, $Pm",
"",
[]>, Sched<[]> {
bits<4> Pg;
bits<4> Pm;
bits<5> Zdn;
let Inst{31-24} = 0b00100101;
let Inst{23-22} = sz8_64;
@ -416,7 +416,7 @@ class sve_int_count_v<bits<2> sz8_64, bits<5> opc, string asm,
let Inst{18-16} = opc{4-2};
let Inst{15-11} = 0b10000;
let Inst{10-9} = opc{1-0};
let Inst{8-5} = Pg;
let Inst{8-5} = Pm;
let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn";
@ -425,9 +425,16 @@ class sve_int_count_v<bits<2> sz8_64, bits<5> opc, string asm,
}
multiclass sve_int_count_v<bits<5> opc, string asm> {
def _H : sve_int_count_v<0b01, opc, asm, ZPR16>;
def _S : sve_int_count_v<0b10, opc, asm, ZPR32>;
def _D : sve_int_count_v<0b11, opc, asm, ZPR64>;
def _H : sve_int_count_v<0b01, opc, asm, ZPR16, PPR16>;
def _S : sve_int_count_v<0b10, opc, asm, ZPR32, PPR32>;
def _D : sve_int_count_v<0b11, opc, asm, ZPR64, PPR64>;
def : InstAlias<asm # "\t$Zdn, $Pm",
(!cast<Instruction>(NAME # "_H") ZPR16:$Zdn, PPRAny:$Pm), 0>;
def : InstAlias<asm # "\t$Zdn, $Pm",
(!cast<Instruction>(NAME # "_S") ZPR32:$Zdn, PPRAny:$Pm), 0>;
def : InstAlias<asm # "\t$Zdn, $Pm",
(!cast<Instruction>(NAME # "_D") ZPR64:$Zdn, PPRAny:$Pm), 0>;
}
class sve_int_pcount_pred<bits<2> sz8_64, bits<4> opc, string asm,

26
llvm/test/MC/AArch64/SVE/decp.s
View File

@ -56,19 +56,37 @@ decp xzr, p15.d
// CHECK-UNKNOWN: ff 89 ed 25 <unknown>
decp z31.h, p15
// CHECK-INST: decp z31.h, p15
// CHECK-INST: decp z31.h, p15.h
// CHECK-ENCODING: [0xff,0x81,0x6d,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 6d 25 <unknown>
decp z31.h, p15.h
// CHECK-INST: decp z31.h, p15.h
// CHECK-ENCODING: [0xff,0x81,0x6d,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 6d 25 <unknown>
decp z31.s, p15
// CHECK-INST: decp z31.s, p15
// CHECK-INST: decp z31.s, p15.s
// CHECK-ENCODING: [0xff,0x81,0xad,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ad 25 <unknown>
decp z31.s, p15.s
// CHECK-INST: decp z31.s, p15.s
// CHECK-ENCODING: [0xff,0x81,0xad,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ad 25 <unknown>
decp z31.d, p15
// CHECK-INST: decp z31.d, p15
// CHECK-INST: decp z31.d, p15.d
// CHECK-ENCODING: [0xff,0x81,0xed,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ed 25 <unknown>
decp z31.d, p15.d
// CHECK-INST: decp z31.d, p15.d
// CHECK-ENCODING: [0xff,0x81,0xed,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ed 25 <unknown>
@ -83,7 +101,7 @@ movprfx z31, z6
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
decp z31.d, p15
decp z31.d, p15.d
// CHECK-INST: decp z31.d, p15
// CHECK-ENCODING: [0xff,0x81,0xed,0x25]
// CHECK-ERROR: instruction requires: sve

28
llvm/test/MC/AArch64/SVE/incp.s
View File

@ -56,19 +56,37 @@ incp xzr, p15.d
// CHECK-UNKNOWN: ff 89 ec 25 <unknown>
incp z31.h, p15
// CHECK-INST: incp z31.h, p15
// CHECK-INST: incp z31.h, p15.h
// CHECK-ENCODING: [0xff,0x81,0x6c,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 6c 25 <unknown>
incp z31.h, p15.h
// CHECK-INST: incp z31.h, p15.h
// CHECK-ENCODING: [0xff,0x81,0x6c,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 6c 25 <unknown>
incp z31.s, p15
// CHECK-INST: incp z31.s, p15
// CHECK-INST: incp z31.s, p15.s
// CHECK-ENCODING: [0xff,0x81,0xac,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ac 25 <unknown>
incp z31.s, p15.s
// CHECK-INST: incp z31.s, p15.s
// CHECK-ENCODING: [0xff,0x81,0xac,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ac 25 <unknown>
incp z31.d, p15
// CHECK-INST: incp z31.d, p15
// CHECK-INST: incp z31.d, p15.d
// CHECK-ENCODING: [0xff,0x81,0xec,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ec 25 <unknown>
incp z31.d, p15.d
// CHECK-INST: incp z31.d, p15.d
// CHECK-ENCODING: [0xff,0x81,0xec,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ec 25 <unknown>
@ -83,8 +101,8 @@ movprfx z31, z6
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
incp z31.d, p15
// CHECK-INST: incp z31.d, p15
incp z31.d, p15.d
// CHECK-INST: incp z31.d, p15.d
// CHECK-ENCODING: [0xff,0x81,0xec,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ec 25 <unknown>

28
llvm/test/MC/AArch64/SVE/sqdecp.s
View File

@ -56,19 +56,37 @@ sqdecp xzr, p15.d, wzr
// CHECK-UNKNOWN: ff 89 ea 25 <unknown>
sqdecp z0.h, p0
// CHECK-INST: sqdecp z0.h, p0
// CHECK-INST: sqdecp z0.h, p0.h
// CHECK-ENCODING: [0x00,0x80,0x6a,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 6a 25 <unknown>
sqdecp z0.h, p0.h
// CHECK-INST: sqdecp z0.h, p0.h
// CHECK-ENCODING: [0x00,0x80,0x6a,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 6a 25 <unknown>
sqdecp z0.s, p0
// CHECK-INST: sqdecp z0.s, p0
// CHECK-INST: sqdecp z0.s, p0.s
// CHECK-ENCODING: [0x00,0x80,0xaa,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 aa 25 <unknown>
sqdecp z0.s, p0.s
// CHECK-INST: sqdecp z0.s, p0.s
// CHECK-ENCODING: [0x00,0x80,0xaa,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 aa 25 <unknown>
sqdecp z0.d, p0
// CHECK-INST: sqdecp z0.d, p0
// CHECK-INST: sqdecp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xea,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 ea 25 <unknown>
sqdecp z0.d, p0.d
// CHECK-INST: sqdecp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xea,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 ea 25 <unknown>
@ -83,8 +101,8 @@ movprfx z0, z7
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sqdecp z0.d, p0
// CHECK-INST: sqdecp z0.d, p0
sqdecp z0.d, p0.d
// CHECK-INST: sqdecp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xea,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 ea 25 <unknown>

28
llvm/test/MC/AArch64/SVE/sqincp.s
View File

@ -56,19 +56,37 @@ sqincp xzr, p15.d, wzr
// CHECK-UNKNOWN: ff 89 e8 25 <unknown>
sqincp z0.h, p0
// CHECK-INST: sqincp z0.h, p0
// CHECK-INST: sqincp z0.h, p0.h
// CHECK-ENCODING: [0x00,0x80,0x68,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 68 25 <unknown>
sqincp z0.h, p0.h
// CHECK-INST: sqincp z0.h, p0.h
// CHECK-ENCODING: [0x00,0x80,0x68,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 68 25 <unknown>
sqincp z0.s, p0
// CHECK-INST: sqincp z0.s, p0
// CHECK-INST: sqincp z0.s, p0.s
// CHECK-ENCODING: [0x00,0x80,0xa8,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 a8 25 <unknown>
sqincp z0.s, p0.s
// CHECK-INST: sqincp z0.s, p0.s
// CHECK-ENCODING: [0x00,0x80,0xa8,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 a8 25 <unknown>
sqincp z0.d, p0
// CHECK-INST: sqincp z0.d, p0
// CHECK-INST: sqincp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xe8,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 e8 25 <unknown>
sqincp z0.d, p0.d
// CHECK-INST: sqincp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xe8,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 e8 25 <unknown>
@ -83,8 +101,8 @@ movprfx z0, z7
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sqincp z0.d, p0
// CHECK-INST: sqincp z0.d, p0
sqincp z0.d, p0.d
// CHECK-INST: sqincp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xe8,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 e8 25 <unknown>

28
llvm/test/MC/AArch64/SVE/uqdecp.s
View File

@ -56,19 +56,37 @@ uqdecp wzr, p15.d
// CHECK-UNKNOWN: ff 89 eb 25 <unknown>
uqdecp z0.h, p0
// CHECK-INST: uqdecp z0.h, p0
// CHECK-INST: uqdecp z0.h, p0.h
// CHECK-ENCODING: [0x00,0x80,0x6b,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 6b 25 <unknown>
uqdecp z0.h, p0.h
// CHECK-INST: uqdecp z0.h, p0.h
// CHECK-ENCODING: [0x00,0x80,0x6b,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 6b 25 <unknown>
uqdecp z0.s, p0
// CHECK-INST: uqdecp z0.s, p0
// CHECK-INST: uqdecp z0.s, p0.s
// CHECK-ENCODING: [0x00,0x80,0xab,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 ab 25 <unknown>
uqdecp z0.s, p0.s
// CHECK-INST: uqdecp z0.s, p0.s
// CHECK-ENCODING: [0x00,0x80,0xab,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 ab 25 <unknown>
uqdecp z0.d, p0
// CHECK-INST: uqdecp z0.d, p0
// CHECK-INST: uqdecp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xeb,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 eb 25 <unknown>
uqdecp z0.d, p0.d
// CHECK-INST: uqdecp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xeb,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 eb 25 <unknown>
@ -83,8 +101,8 @@ movprfx z0, z7
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
uqdecp z0.d, p0
// CHECK-INST: uqdecp z0.d, p0
uqdecp z0.d, p0.d
// CHECK-INST: uqdecp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xeb,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 eb 25 <unknown>

28
llvm/test/MC/AArch64/SVE/uqincp.s
View File

@ -56,19 +56,37 @@ uqincp wzr, p15.d
// CHECK-UNKNOWN: ff 89 e9 25 <unknown>
uqincp z0.h, p0
// CHECK-INST: uqincp z0.h, p0
// CHECK-INST: uqincp z0.h, p0.h
// CHECK-ENCODING: [0x00,0x80,0x69,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 69 25 <unknown>
uqincp z0.h, p0.h
// CHECK-INST: uqincp z0.h, p0.h
// CHECK-ENCODING: [0x00,0x80,0x69,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 69 25 <unknown>
uqincp z0.s, p0
// CHECK-INST: uqincp z0.s, p0
// CHECK-INST: uqincp z0.s, p0.s
// CHECK-ENCODING: [0x00,0x80,0xa9,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 a9 25 <unknown>
uqincp z0.s, p0.s
// CHECK-INST: uqincp z0.s, p0.s
// CHECK-ENCODING: [0x00,0x80,0xa9,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 a9 25 <unknown>
uqincp z0.d, p0
// CHECK-INST: uqincp z0.d, p0
// CHECK-INST: uqincp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xe9,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 e9 25 <unknown>
uqincp z0.d, p0.d
// CHECK-INST: uqincp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xe9,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 e9 25 <unknown>
@ -83,8 +101,8 @@ movprfx z0, z7
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
uqincp z0.d, p0
// CHECK-INST: uqincp z0.d, p0
uqincp z0.d, p0.d
// CHECK-INST: uqincp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xe9,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 e9 25 <unknown>