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AMDGPU: Add test for r308774 

llvm-svn: 309733
This commit is contained in:
Matt Arsenault 2017-08-01 19:54:58 +00:00
parent b62a4eb524
commit a5fcb83bfa
1 changed files with 30 additions and 1 deletions
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31
llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
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@ -1,4 +1,4 @@
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mattr=-promote-alloca -amdgpu-function-calls -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
; Test that non-entry function frame indices are expanded properly to
; give an index relative to the scratch wave offset register
@ -163,4 +163,33 @@ define void @func_other_fi_user_non_inline_imm_offset_i32_vcc_live() #0 {
ret void
}
declare void @func(<4 x float>* nocapture) #0
; undef flag not preserved in eliminateFrameIndex when handling the
; stores in the middle block.
; GCN-LABEL: {{^}}undefined_stack_store_reg:
; GCN: s_and_saveexec_b64
; GCN: buffer_store_dword v0, off, s[0:3], s5 offset:
; GCN: buffer_store_dword v0, off, s[0:3], s5 offset:
; GCN: buffer_store_dword v0, off, s[0:3], s5 offset:
; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s5 offset:
define void @undefined_stack_store_reg(float %arg, i32 %arg1) #0 {
bb:
%tmp = alloca <4 x float>, align 16
%tmp2 = insertelement <4 x float> undef, float %arg, i32 0
store <4 x float> %tmp2, <4 x float>* undef
%tmp3 = icmp eq i32 %arg1, 0
br i1 %tmp3, label %bb4, label %bb5
bb4:
call void @func(<4 x float>* nonnull undef)
store <4 x float> %tmp2, <4 x float>* %tmp, align 16
call void @func(<4 x float>* nonnull %tmp)
br label %bb5
bb5:
ret void
}
attributes #0 = { nounwind }