maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[X86][Costmodel] Load/store i8 Stride=6 VF=32 interleaving costs 

The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3

For load we have:
https://godbolt.org/z/c1jjKqP7b - for intels `Block RThroughput: <=82.0`; for ryzens, `Block RThroughput: <=26.0`
So pick cost of `82`.

For store we have:
https://godbolt.org/z/YM4ErY8x7 - for intels `Block RThroughput: <=90.0`; for ryzens, `Block RThroughput: <=25.5`
So pick cost of `90`.

I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D111013
This commit is contained in:
Roman Lebedev 2021-10-03 23:23:13 +03:00
parent bd5ba437fd
commit a5e5883ef5
No known key found for this signature in database
GPG Key ID: 083C3EBB4A1689E0
3 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
View File

@ -5118,6 +5118,7 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2(
{6, MVT::v4i8, 14}, // (load 24i8 and) deinterleave into 6 x 4i8
{6, MVT::v8i8, 18}, // (load 48i8 and) deinterleave into 6 x 8i8
{6, MVT::v16i8, 43}, // (load 96i8 and) deinterleave into 6 x 16i8
{6, MVT::v32i8, 82}, // (load 192i8 and) deinterleave into 6 x 32i8
{6, MVT::v2i16, 13}, // (load 12i16 and) deinterleave into 6 x 2i16
{6, MVT::v4i16, 9}, // (load 24i16 and) deinterleave into 6 x 4i16
@ -5173,6 +5174,7 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2(
{6, MVT::v4i8, 9}, // interleave 6 x 4i8 into 24i8 (and store)
{6, MVT::v8i8, 16}, // interleave 6 x 8i8 into 48i8 (and store)
{6, MVT::v16i8, 27}, // interleave 6 x 16i8 into 96i8 (and store)
{6, MVT::v32i8, 90}, // interleave 6 x 32i8 into 192i8 (and store)
{6, MVT::v2i16, 10}, // interleave 6 x 2i16 into 12i16 (and store)
{6, MVT::v4i16, 15}, // interleave 6 x 4i16 into 24i16 (and store)

2
llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-6.ll
View File

@ -30,7 +30,7 @@ target triple = "x86_64-unknown-linux-gnu"
; AVX2: LV: Found an estimated cost of 17 for VF 4 For instruction: %v0 = load i8, i8* %in0, align 1
; AVX2: LV: Found an estimated cost of 20 for VF 8 For instruction: %v0 = load i8, i8* %in0, align 1
; AVX2: LV: Found an estimated cost of 46 for VF 16 For instruction: %v0 = load i8, i8* %in0, align 1
; AVX2: LV: Found an estimated cost of 498 for VF 32 For instruction: %v0 = load i8, i8* %in0, align 1
; AVX2: LV: Found an estimated cost of 88 for VF 32 For instruction: %v0 = load i8, i8* %in0, align 1
;
; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction: %v0 = load i8, i8* %in0, align 1
; AVX512: LV: Found an estimated cost of 7 for VF 2 For instruction: %v0 = load i8, i8* %in0, align 1

2
llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-6.ll
View File

@ -30,7 +30,7 @@ target triple = "x86_64-unknown-linux-gnu"
; AVX2: LV: Found an estimated cost of 12 for VF 4 For instruction: store i8 %v5, i8* %out5, align 1
; AVX2: LV: Found an estimated cost of 18 for VF 8 For instruction: store i8 %v5, i8* %out5, align 1
; AVX2: LV: Found an estimated cost of 30 for VF 16 For instruction: store i8 %v5, i8* %out5, align 1
; AVX2: LV: Found an estimated cost of 498 for VF 32 For instruction: store i8 %v5, i8* %out5, align 1
; AVX2: LV: Found an estimated cost of 96 for VF 32 For instruction: store i8 %v5, i8* %out5, align 1
;
; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction: store i8 %v5, i8* %out5, align 1
; AVX512: LV: Found an estimated cost of 18 for VF 2 For instruction: store i8 %v5, i8* %out5, align 1