forked from OSchip/llvm-project
[X86] Fix tile config register spill issue.
This is an optimized approach for D94155. Previous code build the model that tile config register is the user of each AMX instruction. There is a problem for the tile config register spill. When across function, the ldtilecfg instruction may be inserted on each AMX instruction which use tile config register. This cause all tile data register clobber. To fix this issue, we remove the model of tile config register. Instead, we analyze the AMX instructions between one call to another. We will insert ldtilecfg after the first call if we find any AMX instructions. Reviewed By: LuoYuanke Differential Revision: https://reviews.llvm.org/D95136
This commit is contained in:
Wang, Pengfei
parent
c32f399802
commit
a5d9e0c79b
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@ -461,25 +461,13 @@ bool X86ExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
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case TargetOpcode::ICALL_BRANCH_FUNNEL:
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ExpandICallBranchFunnel(&MBB, MBBI);
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return true;
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case X86::PLDTILECFG: {
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MI.RemoveOperand(0);
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MI.setDesc(TII->get(X86::LDTILECFG));
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return true;
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}
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case X86::PSTTILECFG: {
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MI.RemoveOperand(MI.getNumOperands() - 1); // Remove $tmmcfg
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MI.setDesc(TII->get(X86::STTILECFG));
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return true;
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}
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case X86::PTILELOADDV: {
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MI.RemoveOperand(8); // Remove $tmmcfg
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for (unsigned i = 2; i > 0; --i)
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MI.RemoveOperand(i);
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MI.setDesc(TII->get(X86::TILELOADD));
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return true;
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}
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case X86::PTDPBSSDV: {
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MI.RemoveOperand(7); // Remove $tmmcfg
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MI.untieRegOperand(4);
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for (unsigned i = 3; i > 0; --i)
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MI.RemoveOperand(i);
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@ -488,14 +476,13 @@ bool X86ExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
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return true;
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}
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case X86::PTILESTOREDV: {
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MI.RemoveOperand(8); // Remove $tmmcfg
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for (int i = 1; i >= 0; --i)
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MI.RemoveOperand(i);
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MI.setDesc(TII->get(X86::TILESTORED));
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return true;
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}
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case X86::PTILEZEROV: {
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for (int i = 3; i > 0; --i) // Remove row, col, $tmmcfg
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for (int i = 2; i > 0; --i) // Remove row, col
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MI.RemoveOperand(i);
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MI.setDesc(TII->get(X86::TILEZERO));
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return true;
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@ -2094,8 +2094,12 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF,
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// Emit tilerelease for AMX kernel.
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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if (!MRI.reg_nodbg_empty(X86::TMMCFG))
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const TargetRegisterClass *RC = TRI->getRegClass(X86::TILERegClassID);
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for (unsigned I = 0; I < RC->getNumRegs(); I++)
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if (!MRI.reg_nodbg_empty(X86::TMM0 + I)) {
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BuildMI(MBB, Terminator, DL, TII.get(X86::TILERELEASE));
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break;
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}
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}
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StackOffset X86FrameLowering::getFrameIndexReference(const MachineFunction &MF,
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@ -4607,7 +4607,6 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
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SDValue Index = Node->getOperand(5);
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SDValue Disp = CurDAG->getTargetConstant(0, dl, MVT::i32);
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SDValue Segment = CurDAG->getRegister(0, MVT::i16);
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SDValue CFG = CurDAG->getRegister(0, MVT::Untyped);
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SDValue Chain = Node->getOperand(0);
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MachineSDNode *CNode;
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SDValue Ops[] = {Node->getOperand(2),
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@ -4617,7 +4616,6 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
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Index,
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Disp,
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Segment,
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CFG,
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Chain};
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CNode = CurDAG->getMachineNode(Opc, dl, {MVT::x86amx, MVT::Other}, Ops);
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ReplaceNode(Node, CNode);
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@ -4628,14 +4626,12 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
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break;
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SDValue Chain = Node->getOperand(0);
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unsigned Opc = X86::PTDPBSSDV;
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SDValue CFG = CurDAG->getRegister(0, MVT::Untyped);
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SDValue Ops[] = {Node->getOperand(2),
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Node->getOperand(3),
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Node->getOperand(4),
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Node->getOperand(5),
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Node->getOperand(6),
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Node->getOperand(7),
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CFG,
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Chain};
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MachineSDNode *CNode =
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CurDAG->getMachineNode(Opc, dl, {MVT::x86amx, MVT::Other}, Ops);
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@ -4647,8 +4643,7 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
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break;
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unsigned Opc = X86::PTILEZEROV;
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SDValue Chain = Node->getOperand(0);
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SDValue CFG = CurDAG->getRegister(0, MVT::Untyped);
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SDValue Ops[] = {Node->getOperand(2), Node->getOperand(3), CFG, Chain};
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SDValue Ops[] = {Node->getOperand(2), Node->getOperand(3), Chain};
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MachineSDNode *CNode =
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CurDAG->getMachineNode(Opc, dl, {MVT::x86amx, MVT::Other}, Ops);
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ReplaceNode(Node, CNode);
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@ -4719,7 +4714,6 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
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SDValue Index = Node->getOperand(5);
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SDValue Disp = CurDAG->getTargetConstant(0, dl, MVT::i32);
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SDValue Segment = CurDAG->getRegister(0, MVT::i16);
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SDValue CFG = CurDAG->getRegister(0, MVT::Untyped);
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SDValue Chain = Node->getOperand(0);
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MachineSDNode *CNode;
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SDValue Ops[] = {Node->getOperand(2),
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@ -4730,7 +4724,6 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
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Disp,
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Segment,
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Node->getOperand(6),
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CFG,
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Chain};
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CNode = CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops);
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ReplaceNode(Node, CNode);
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@ -48,23 +48,14 @@ let Predicates = [HasAMXTILE, In64BitMode] in {
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VEX, T8XD;
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// Pseduo instruction for RA.
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let hasSideEffects = 1, mayLoad = 1,
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Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in
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def PLDTILECFG : PseudoI <(outs TILECFG:$cfg), (ins opaquemem:$src), []>;
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let hasSideEffects = 1, mayStore = 1 in
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def PSTTILECFG : PseudoI<(outs), (ins opaquemem:$dst, TILECFG:$cfg), []>;
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def PTILELOADDV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,
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GR16:$src2,
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opaquemem:$src3,
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TILECFG:$cfg), []>;
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opaquemem:$src3), []>;
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def PTILESTOREDV : PseudoI<(outs), (ins GR16:$src1,
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GR16:$src2, opaquemem:$src3,
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TILE:$src4, TILECFG:$cfg), []>;
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TILE:$src4), []>;
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def PTILEZEROV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,
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GR16:$src2,
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TILECFG:$cfg), []>;
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GR16:$src2), []>;
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let usesCustomInserter = 1 in {
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// Pseudo instructions, using immediates instead of tile registers.
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@ -104,7 +95,7 @@ let Predicates = [HasAMXINT8, In64BitMode] in {
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let Constraints = "$src4 = $dst" in
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def PTDPBSSDV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,
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GR16:$src2, GR16:$src3, TILE:$src4,
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TILE:$src5, TILE:$src6, TILECFG:$cfg), []>;
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TILE:$src5, TILE:$src6), []>;
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let usesCustomInserter = 1 in {
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// Pseudo instructions, using immediates instead of tile registers.
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@ -3808,10 +3808,6 @@ void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineOperand &MO = NewMI->getOperand(2);
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MO.setReg(VirtReg);
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MO.setIsKill(true);
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} else if (RC->getID() == X86::TILECFGRegClassID) {
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unsigned Opc = X86::PSTTILECFG;
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addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
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.addReg(SrcReg, getKillRegState(isKill));
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} else {
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unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
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bool isAligned =
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@ -3840,10 +3836,6 @@ void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineOperand &MO = NewMI->getOperand(3);
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MO.setReg(VirtReg);
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MO.setIsKill(true);
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} else if (RC->getID() == X86::TILECFGRegClassID) {
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unsigned Opc = X86::PLDTILECFG;
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addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg),
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FrameIdx);
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} else {
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const MachineFunction &MF = *MBB.getParent();
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unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
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@ -6789,7 +6781,7 @@ bool X86InstrInfo::isSchedulingBoundary(const MachineInstr &MI,
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// ENDBR instructions should not be scheduled around.
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unsigned Opcode = MI.getOpcode();
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if (Opcode == X86::ENDBR64 || Opcode == X86::ENDBR32 ||
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Opcode == X86::PLDTILECFG)
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Opcode == X86::LDTILECFG)
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return true;
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return TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF);
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@ -98,9 +98,8 @@ void X86PreTileConfig::getAnalysisUsage(AnalysisUsage &AU) const {
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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static Register buildConfigMI(MachineBasicBlock::iterator MI, int FrameIdx,
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const TargetInstrInfo *TII,
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MachineRegisterInfo *MRI,
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static void buildConfigMI(MachineBasicBlock::iterator MI, int FrameIdx,
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const TargetInstrInfo *TII, MachineRegisterInfo *MRI,
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const X86Subtarget *ST) {
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auto *MBB = MI->getParent();
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@ -117,12 +116,8 @@ static Register buildConfigMI(MachineBasicBlock::iterator MI, int FrameIdx,
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}
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// build psuedo ldtilecfg
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Register VReg = MRI->createVirtualRegister(&X86::TILECFGRegClass);
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addFrameReference(
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BuildMI(*MBB, MI, DebugLoc(), TII->get(X86::PLDTILECFG), VReg), FrameIdx);
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return VReg;
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addFrameReference(BuildMI(*MBB, MI, DebugLoc(), TII->get(X86::LDTILECFG)),
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FrameIdx);
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}
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static ShapeT getShape(const MachineInstr &MI, MachineRegisterInfo *MRI) {
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@ -219,25 +214,97 @@ MachineInstr *X86PreTileConfig::getTileConfigPoint() {
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return &*MII;
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}
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static void addTileCFGUse(MachineFunction &MF, Register CFG) {
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for (MachineBasicBlock &MBB : MF) {
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// Traverse the basic block.
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for (MachineInstr &MI : MBB) {
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unsigned Opcode = MI.getOpcode();
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switch (Opcode) {
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static bool isAMXInstruction(MachineBasicBlock::iterator MII) {
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switch (MII->getOpcode()) {
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default:
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break;
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return false;
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case X86::PTILELOADDV:
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case X86::PTILESTOREDV:
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case X86::PTDPBSSDV:
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case X86::PTILEZEROV:
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unsigned NumOperands = MI.getNumOperands();
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MI.RemoveOperand(NumOperands - 1);
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MI.addOperand(MF, MachineOperand::CreateReg(CFG, false));
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break;
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return true;
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}
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}
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struct BBInfo {
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bool HasAMX = false;
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bool HasCallBeforeAMX = false;
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bool HasAMXBeforeCallInSuccs = false;
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MachineInstr *LastCall = nullptr;
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BBInfo() = default;
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BBInfo(SmallSet<MachineInstr *, 8> &CfgNeedInsert, MachineBasicBlock *MBB,
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MachineInstr *MI = nullptr) {
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MachineBasicBlock::iterator MII = MI ? MI->getIterator() : MBB->begin();
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for (auto E = MBB->end(); MII != E; ++MII) {
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if (isAMXInstruction(MII)) {
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HasAMX = true;
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if (LastCall)
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CfgNeedInsert.insert(LastCall);
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} else if (MII->isCall()) {
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LastCall = &*MII;
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if (!HasAMX)
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HasCallBeforeAMX = true;
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}
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}
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}
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};
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static void reloadTileConfig(MachineInstr *MI, int FI,
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const TargetInstrInfo *TII,
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const TargetRegisterInfo *TRI) {
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SmallSet<MachineInstr *, 8> CfgNeedInsert;
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SmallVector<MachineBasicBlock *, 8> WorkList;
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DenseMap<MachineBasicBlock *, BBInfo> BBVisitedInfo;
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MachineBasicBlock *MBB = MI->getParent();
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BBVisitedInfo[MBB] = BBInfo(CfgNeedInsert, MBB, MI);
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WorkList.push_back(MBB);
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while (!WorkList.empty()) {
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MBB = WorkList.pop_back_val();
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for (auto I = MBB->succ_begin(), E = MBB->succ_end(); I != E; ++I) {
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if (!BBVisitedInfo.count(*I)) {
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BBVisitedInfo[*I] = BBInfo(CfgNeedInsert, *I);
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WorkList.push_back(*I);
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}
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}
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}
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WorkList.clear();
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for (auto I : BBVisitedInfo) {
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WorkList.push_back(I.first);
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while (!WorkList.empty()) {
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MBB = WorkList.pop_back_val();
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if (BBVisitedInfo[MBB].HasCallBeforeAMX ||
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(!BBVisitedInfo[MBB].HasAMX &&
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!BBVisitedInfo[MBB].HasAMXBeforeCallInSuccs))
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continue;
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for (auto I = MBB->pred_begin(), E = MBB->pred_end(); I != E; ++I) {
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if (!BBVisitedInfo.count(*I) ||
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BBVisitedInfo[*I].HasAMXBeforeCallInSuccs)
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continue;
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if (BBVisitedInfo[*I].LastCall)
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CfgNeedInsert.insert(BBVisitedInfo[*I].LastCall);
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BBVisitedInfo[*I].HasAMXBeforeCallInSuccs = true;
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WorkList.push_back(*I);
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}
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}
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}
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for (auto *I : CfgNeedInsert) {
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BitVector UsableRegs(TRI->getNumRegs());
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const TargetRegisterClass *RC = TRI->getRegClass(X86::TILERegClassID);
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for (unsigned J = 0; J < RC->getNumRegs(); J++)
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UsableRegs.set(X86::TMM0 + J);
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for (MachineOperand &CallMO : I->operands()) {
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if (CallMO.isRegMask())
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UsableRegs.clearBitsInMask(CallMO.getRegMask());
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}
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if (!UsableRegs.none())
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addFrameReference(BuildMI(*I->getParent(), ++I->getIterator(), DebugLoc(),
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TII->get(X86::LDTILECFG)),
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FI);
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}
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}
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@ -255,8 +322,8 @@ bool X86PreTileConfig::runOnMachineFunction(MachineFunction &mf) {
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unsigned Size = ST->getTileConfigSize();
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Align Alignment = ST->getTileConfigAlignment();
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int SS = mf.getFrameInfo().CreateStackObject(Size, Alignment, false);
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Register CFG = buildConfigMI(MI, SS, TII, MRI, ST);
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addTileCFGUse(mf, CFG);
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buildConfigMI(MI, SS, TII, MRI, ST);
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reloadTileConfig(MI, SS, TII, TRI);
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return true;
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}
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@ -639,8 +639,3 @@ def BNDR : RegisterClass<"X86", [v2i64], 128, (sequence "BND%u", 0, 3)>;
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let CopyCost = -1 in // Don't allow copying of tile registers
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def TILE : RegisterClass<"X86", [x86amx], 8192,
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(sequence "TMM%u", 0, 7)> {let Size = 8192;}
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def TILECFG : RegisterClass<"X86", [untyped], 512, (add TMMCFG)> {
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let CopyCost = -1; // Don't allow copying of tile config registers.
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let isAllocatable = 1;
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let Size = 512;
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}
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@ -22,6 +22,7 @@
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#include "X86MachineFunctionInfo.h"
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#include "X86RegisterInfo.h"
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#include "X86Subtarget.h"
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#include "llvm/ADT/PostOrderIterator.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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@ -130,13 +131,14 @@ static MachineInstr *storeImmToStackSlot(MachineBasicBlock &MBB,
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}
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MachineInstr *X86TileConfig::getTileConfigPoint() {
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for (MachineBasicBlock &MBB : *MF) {
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// Traverse the basic block.
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for (MachineInstr &MI : MBB)
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MachineBasicBlock *Entry = &*MF->begin();
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ReversePostOrderTraversal<MachineBasicBlock *> RPOT(Entry);
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for (MachineBasicBlock *MBB : RPOT) {
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for (MachineInstr &MI : *MBB)
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// Refer X86PreTileConfig.cpp.
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// We only support one tile config for now.
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if (MI.getOpcode() == X86::PLDTILECFG)
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// We only support one tile config for now. The other ldtilecfg
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// is for spill purpose and is dominated by the first ldtilecfg.
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if (MI.getOpcode() == X86::LDTILECFG)
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return &MI;
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}
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@ -148,7 +150,7 @@ void X86TileConfig::tileConfig() {
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if (!MI)
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return;
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MachineBasicBlock *MBB = MI->getParent();
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int SS = MI->getOperand(1).getIndex();
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int SS = MI->getOperand(0).getIndex();
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BitVector PhysRegs(TRI->getNumRegs());
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// Fill in the palette first.
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@ -1,10 +1,21 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-int8 -mattr=+avx512f -verify-machineinstrs | FileCheck %s
|
||||
|
||||
%struct.__tile_str = type <{ i16, i16, [60 x i8], <256 x i32> }>
|
||||
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-int8 -mattr=+avx512f -verify-machineinstrs -enable-ipra | FileCheck -check-prefix=IPRA %s
|
||||
|
||||
@buf = dso_local global [3072 x i8] zeroinitializer, align 64
|
||||
|
||||
define internal void @foo() {
|
||||
; CHECK-LABEL: foo:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: retq
|
||||
;
|
||||
; IPRA-LABEL: foo:
|
||||
; IPRA: # %bb.0: # %entry
|
||||
; IPRA-NEXT: retq
|
||||
entry:
|
||||
ret void
|
||||
}
|
||||
|
||||
define dso_local void @test_api(i16 signext %0, i16 signext %1) nounwind {
|
||||
; CHECK-LABEL: test_api:
|
||||
; CHECK: # %bb.0:
|
||||
|
|
@ -25,7 +36,6 @@ define dso_local void @test_api(i16 signext %0, i16 signext %1) nounwind {
|
|||
; CHECK-NEXT: movb $8, {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movw %bx, {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: sttilecfg {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Folded Spill
|
||||
; CHECK-NEXT: movl $buf, %eax
|
||||
; CHECK-NEXT: movl $32, %r14d
|
||||
; CHECK-NEXT: movw $8, %r15w
|
||||
|
|
@ -36,11 +46,10 @@ define dso_local void @test_api(i16 signext %0, i16 signext %1) nounwind {
|
|||
; CHECK-NEXT: tileloadd (%rax,%r14), %tmm2
|
||||
; CHECK-NEXT: movabsq $64, %rax
|
||||
; CHECK-NEXT: tilestored %tmm2, 1024(%rsp,%rax) # 1024-byte Folded Spill
|
||||
; CHECK-NEXT: xorl %eax, %eax
|
||||
; CHECK-NEXT: vzeroupper
|
||||
; CHECK-NEXT: callq foo
|
||||
; CHECK-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movl $buf+2048, %eax
|
||||
; CHECK-NEXT: ldtilecfg {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Folded Reload
|
||||
; CHECK-NEXT: tileloadd (%rax,%r14), %tmm0
|
||||
; CHECK-NEXT: movabsq $64, %rcx
|
||||
; CHECK-NEXT: tileloadd 2048(%rsp,%rcx), %tmm1 # 1024-byte Folded Reload
|
||||
|
|
@ -55,16 +64,204 @@ define dso_local void @test_api(i16 signext %0, i16 signext %1) nounwind {
|
|||
; CHECK-NEXT: popq %rbp
|
||||
; CHECK-NEXT: tilerelease
|
||||
; CHECK-NEXT: retq
|
||||
;
|
||||
; IPRA-LABEL: test_api:
|
||||
; IPRA: # %bb.0:
|
||||
; IPRA-NEXT: subq $72, %rsp
|
||||
; IPRA-NEXT: vpxord %zmm0, %zmm0, %zmm0
|
||||
; IPRA-NEXT: vmovdqu64 %zmm0, {{[0-9]+}}(%rsp)
|
||||
; IPRA-NEXT: movb $1, {{[0-9]+}}(%rsp)
|
||||
; IPRA-NEXT: movb %dil, {{[0-9]+}}(%rsp)
|
||||
; IPRA-NEXT: movw $8, {{[0-9]+}}(%rsp)
|
||||
; IPRA-NEXT: movb $8, {{[0-9]+}}(%rsp)
|
||||
; IPRA-NEXT: movw %si, {{[0-9]+}}(%rsp)
|
||||
; IPRA-NEXT: movb %dil, {{[0-9]+}}(%rsp)
|
||||
; IPRA-NEXT: movw %si, {{[0-9]+}}(%rsp)
|
||||
; IPRA-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
|
||||
; IPRA-NEXT: movl $buf, %eax
|
||||
; IPRA-NEXT: movl $32, %ecx
|
||||
; IPRA-NEXT: movw $8, %dx
|
||||
; IPRA-NEXT: tileloadd (%rax,%rcx), %tmm0
|
||||
; IPRA-NEXT: movl $buf+1024, %eax
|
||||
; IPRA-NEXT: tileloadd (%rax,%rcx), %tmm1
|
||||
; IPRA-NEXT: callq foo
|
||||
; IPRA-NEXT: movl $buf+2048, %eax
|
||||
; IPRA-NEXT: tileloadd (%rax,%rcx), %tmm2
|
||||
; IPRA-NEXT: tdpbssd %tmm1, %tmm0, %tmm2
|
||||
; IPRA-NEXT: tilestored %tmm2, (%rax,%rcx)
|
||||
; IPRA-NEXT: addq $72, %rsp
|
||||
; IPRA-NEXT: tilerelease
|
||||
; IPRA-NEXT: vzeroupper
|
||||
; IPRA-NEXT: retq
|
||||
%3 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 %0, i16 8, i8* getelementptr inbounds ([3072 x i8], [3072 x i8]* @buf, i64 0, i64 0), i64 32)
|
||||
%4 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 8, i16 %1, i8* getelementptr inbounds ([3072 x i8], [3072 x i8]* @buf, i64 0, i64 1024), i64 32)
|
||||
tail call void (...) @foo()
|
||||
call void @foo()
|
||||
%5 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 %0, i16 %1, i8* getelementptr inbounds ([3072 x i8], [3072 x i8]* @buf, i64 0, i64 2048), i64 32)
|
||||
%6 = tail call x86_amx @llvm.x86.tdpbssd.internal(i16 %0, i16 %1, i16 8, x86_amx %5, x86_amx %3, x86_amx %4)
|
||||
tail call void @llvm.x86.tilestored64.internal(i16 %0, i16 %1, i8* getelementptr inbounds ([3072 x i8], [3072 x i8]* @buf, i64 0, i64 2048), i64 32, x86_amx %6)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare dso_local void @foo(...)
|
||||
define dso_local i32 @test_loop(i32 %0) nounwind {
|
||||
; CHECK-LABEL: test_loop:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: pushq %rbp
|
||||
; CHECK-NEXT: pushq %r15
|
||||
; CHECK-NEXT: pushq %r14
|
||||
; CHECK-NEXT: pushq %r13
|
||||
; CHECK-NEXT: pushq %r12
|
||||
; CHECK-NEXT: pushq %rbx
|
||||
; CHECK-NEXT: subq $3016, %rsp # imm = 0xBC8
|
||||
; CHECK-NEXT: movl %edi, %r14d
|
||||
; CHECK-NEXT: callq foo
|
||||
; CHECK-NEXT: vpxord %zmm0, %zmm0, %zmm0
|
||||
; CHECK-NEXT: vmovdqu64 %zmm0, {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movb $1, {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movb $8, {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movw $8, {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: testl %r14d, %r14d
|
||||
; CHECK-NEXT: jg .LBB2_4
|
||||
; CHECK-NEXT: # %bb.1: # %.preheader
|
||||
; CHECK-NEXT: movl $7, %ebp
|
||||
; CHECK-NEXT: movl $buf, %r15d
|
||||
; CHECK-NEXT: movl $32, %r12d
|
||||
; CHECK-NEXT: movw $8, %bx
|
||||
; CHECK-NEXT: movl $buf+2048, %r13d
|
||||
; CHECK-NEXT: .p2align 4, 0x90
|
||||
; CHECK-NEXT: .LBB2_2: # =>This Inner Loop Header: Depth=1
|
||||
; CHECK-NEXT: tileloadd (%r15,%r12), %tmm0
|
||||
; CHECK-NEXT: movabsq $64, %rax
|
||||
; CHECK-NEXT: tilestored %tmm0, 1024(%rsp,%rax) # 1024-byte Folded Spill
|
||||
; CHECK-NEXT: vzeroupper
|
||||
; CHECK-NEXT: callq foo
|
||||
; CHECK-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movabsq $64, %rax
|
||||
; CHECK-NEXT: tileloadd 1024(%rsp,%rax), %tmm0 # 1024-byte Folded Reload
|
||||
; CHECK-NEXT: tilestored %tmm0, (%r13,%r12)
|
||||
; CHECK-NEXT: callq foo
|
||||
; CHECK-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: decl %ebp
|
||||
; CHECK-NEXT: cmpl $7, %ebp
|
||||
; CHECK-NEXT: jne .LBB2_2
|
||||
; CHECK-NEXT: # %bb.3:
|
||||
; CHECK-NEXT: cmpl $3, %r14d
|
||||
; CHECK-NEXT: jne .LBB2_4
|
||||
; CHECK-NEXT: # %bb.6:
|
||||
; CHECK-NEXT: testl %ebp, %ebp
|
||||
; CHECK-NEXT: jne .LBB2_5
|
||||
; CHECK-NEXT: # %bb.7:
|
||||
; CHECK-NEXT: incl %r14d
|
||||
; CHECK-NEXT: jmp .LBB2_8
|
||||
; CHECK-NEXT: .LBB2_4:
|
||||
; CHECK-NEXT: vzeroupper
|
||||
; CHECK-NEXT: callq foo
|
||||
; CHECK-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movl $32, %eax
|
||||
; CHECK-NEXT: movl $buf+1024, %ecx
|
||||
; CHECK-NEXT: movw $8, %dx
|
||||
; CHECK-NEXT: tileloadd (%rcx,%rax), %tmm0
|
||||
; CHECK-NEXT: tilestored %tmm0, (%rcx,%rax)
|
||||
; CHECK-NEXT: .LBB2_5:
|
||||
; CHECK-NEXT: decl %r14d
|
||||
; CHECK-NEXT: .LBB2_8:
|
||||
; CHECK-NEXT: movl %r14d, %eax
|
||||
; CHECK-NEXT: addq $3016, %rsp # imm = 0xBC8
|
||||
; CHECK-NEXT: popq %rbx
|
||||
; CHECK-NEXT: popq %r12
|
||||
; CHECK-NEXT: popq %r13
|
||||
; CHECK-NEXT: popq %r14
|
||||
; CHECK-NEXT: popq %r15
|
||||
; CHECK-NEXT: popq %rbp
|
||||
; CHECK-NEXT: tilerelease
|
||||
; CHECK-NEXT: retq
|
||||
;
|
||||
; IPRA-LABEL: test_loop:
|
||||
; IPRA: # %bb.0:
|
||||
; IPRA-NEXT: subq $72, %rsp
|
||||
; IPRA-NEXT: movl %edi, %eax
|
||||
; IPRA-NEXT: callq foo
|
||||
; IPRA-NEXT: vpxord %zmm0, %zmm0, %zmm0
|
||||
; IPRA-NEXT: vmovdqu64 %zmm0, {{[0-9]+}}(%rsp)
|
||||
; IPRA-NEXT: movb $1, {{[0-9]+}}(%rsp)
|
||||
; IPRA-NEXT: movb $8, {{[0-9]+}}(%rsp)
|
||||
; IPRA-NEXT: movw $8, {{[0-9]+}}(%rsp)
|
||||
; IPRA-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
|
||||
; IPRA-NEXT: testl %edi, %edi
|
||||
; IPRA-NEXT: jg .LBB2_4
|
||||
; IPRA-NEXT: # %bb.1: # %.preheader
|
||||
; IPRA-NEXT: movl $7, %ecx
|
||||
; IPRA-NEXT: movl $buf, %r8d
|
||||
; IPRA-NEXT: movl $32, %esi
|
||||
; IPRA-NEXT: movw $8, %di
|
||||
; IPRA-NEXT: movl $buf+2048, %edx
|
||||
; IPRA-NEXT: .p2align 4, 0x90
|
||||
; IPRA-NEXT: .LBB2_2: # =>This Inner Loop Header: Depth=1
|
||||
; IPRA-NEXT: tileloadd (%r8,%rsi), %tmm0
|
||||
; IPRA-NEXT: callq foo
|
||||
; IPRA-NEXT: tilestored %tmm0, (%rdx,%rsi)
|
||||
; IPRA-NEXT: callq foo
|
||||
; IPRA-NEXT: decl %ecx
|
||||
; IPRA-NEXT: cmpl $7, %ecx
|
||||
; IPRA-NEXT: jne .LBB2_2
|
||||
; IPRA-NEXT: # %bb.3:
|
||||
; IPRA-NEXT: cmpl $3, %eax
|
||||
; IPRA-NEXT: jne .LBB2_4
|
||||
; IPRA-NEXT: # %bb.6:
|
||||
; IPRA-NEXT: testl %ecx, %ecx
|
||||
; IPRA-NEXT: jne .LBB2_5
|
||||
; IPRA-NEXT: # %bb.7:
|
||||
; IPRA-NEXT: incl %eax
|
||||
; IPRA-NEXT: jmp .LBB2_8
|
||||
; IPRA-NEXT: .LBB2_4:
|
||||
; IPRA-NEXT: callq foo
|
||||
; IPRA-NEXT: movl $32, %ecx
|
||||
; IPRA-NEXT: movl $buf+1024, %edx
|
||||
; IPRA-NEXT: movw $8, %si
|
||||
; IPRA-NEXT: tileloadd (%rdx,%rcx), %tmm0
|
||||
; IPRA-NEXT: tilestored %tmm0, (%rdx,%rcx)
|
||||
; IPRA-NEXT: .LBB2_5:
|
||||
; IPRA-NEXT: decl %eax
|
||||
; IPRA-NEXT: .LBB2_8:
|
||||
; IPRA-NEXT: addq $72, %rsp
|
||||
; IPRA-NEXT: tilerelease
|
||||
; IPRA-NEXT: vzeroupper
|
||||
; IPRA-NEXT: retq
|
||||
call void @foo()
|
||||
br label %2
|
||||
2:
|
||||
%3 = icmp sgt i32 %0, 0
|
||||
br i1 %3, label %11, label %6
|
||||
4:
|
||||
%5 = icmp eq i32 %0, 3
|
||||
br i1 %5, label %13, label %11
|
||||
6:
|
||||
%7 = phi i32 [ %9, %6 ], [ 0, %2 ]
|
||||
%8 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 8, i16 8, i8* getelementptr inbounds ([3072 x i8], [3072 x i8]* @buf, i64 0, i64 0), i64 32)
|
||||
call void @foo()
|
||||
tail call void @llvm.x86.tilestored64.internal(i16 8, i16 8, i8* getelementptr inbounds ([3072 x i8], [3072 x i8]* @buf, i64 0, i64 2048), i64 32, x86_amx %8)
|
||||
call void @foo()
|
||||
%9 = add i32 %7, 1
|
||||
%10 = icmp eq i32 %9, 0
|
||||
br i1 %10, label %4, label %6
|
||||
11:
|
||||
call void @foo()
|
||||
%12 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 8, i16 8, i8* getelementptr inbounds ([3072 x i8], [3072 x i8]* @buf, i64 0, i64 1024), i64 32)
|
||||
tail call void @llvm.x86.tilestored64.internal(i16 8, i16 8, i8* getelementptr inbounds ([3072 x i8], [3072 x i8]* @buf, i64 0, i64 1024), i64 32, x86_amx %12)
|
||||
br label %17
|
||||
13:
|
||||
%14 = icmp eq i32 %9, 7
|
||||
br i1 %14, label %15, label %17
|
||||
15:
|
||||
%16 = add i32 %0, 1
|
||||
br label %19
|
||||
17:
|
||||
%18 = sub i32 %0, 1
|
||||
br label %19
|
||||
19:
|
||||
%20 = phi i32 [ %16, %15 ], [ %18, %17 ]
|
||||
ret i32 %20
|
||||
}
|
||||
|
||||
declare x86_amx @llvm.x86.tileloadd64.internal(i16, i16, i8*, i64)
|
||||
declare x86_amx @llvm.x86.tdpbssd.internal(i16, i16, i16, x86_amx, x86_amx, x86_amx)
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@ define void @test_amx() {
|
|||
; CHECK-LABEL: test_amx:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: tdpbf16ps %tmm7, %tmm4, %tmm3
|
||||
; CHECK-NEXT: tilerelease
|
||||
; CHECK-NEXT: retq
|
||||
call void @llvm.x86.tdpbf16ps(i8 3, i8 4, i8 7)
|
||||
ret void
|
||||
|
|
|
|||
|
|
@ -0,0 +1,123 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-int8 -mattr=+avx512f -verify-machineinstrs | FileCheck %s
|
||||
@buf = dso_local global [3072 x i8] zeroinitializer, align 16
|
||||
|
||||
define dso_local void @test1(i16 signext %0, i16 signext %1) nounwind {
|
||||
; CHECK-LABEL: test1:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vpxord %zmm0, %zmm0, %zmm0
|
||||
; CHECK-NEXT: vmovdqu64 %zmm0, -{{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movb $1, -{{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movw $8, -{{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movb $8, -{{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movw %si, -{{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movw %si, -{{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: ldtilecfg -{{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movl $buf, %eax
|
||||
; CHECK-NEXT: movl $32, %ecx
|
||||
; CHECK-NEXT: movw $8, %dx
|
||||
; CHECK-NEXT: tileloadd (%rax,%rcx), %tmm0
|
||||
; CHECK-NEXT: movl $buf+1024, %eax
|
||||
; CHECK-NEXT: tileloadd (%rax,%rcx), %tmm1
|
||||
; CHECK-NEXT: movl $buf+2048, %eax
|
||||
; CHECK-NEXT: tileloadd (%rax,%rcx), %tmm2
|
||||
; CHECK-NEXT: tdpbssd %tmm1, %tmm0, %tmm2
|
||||
; CHECK-NEXT: tilestored %tmm2, (%rax,%rcx)
|
||||
; CHECK-NEXT: tilerelease
|
||||
; CHECK-NEXT: vzeroupper
|
||||
; CHECK-NEXT: jmp foo # TAILCALL
|
||||
%3 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 %0, i16 8, i8* getelementptr inbounds ([3072 x i8], [3072 x i8]* @buf, i64 0, i64 0), i64 32)
|
||||
%4 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 8, i16 %1, i8* getelementptr inbounds ([3072 x i8], [3072 x i8]* @buf, i64 0, i64 1024), i64 32)
|
||||
%5 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 %0, i16 %1, i8* getelementptr inbounds ([3072 x i8], [3072 x i8]* @buf, i64 0, i64 2048), i64 32)
|
||||
%6 = tail call x86_amx @llvm.x86.tdpbssd.internal(i16 %0, i16 %1, i16 8, x86_amx %5, x86_amx %3, x86_amx %4)
|
||||
tail call void @llvm.x86.tilestored64.internal(i16 %0, i16 %1, i8* getelementptr inbounds ([3072 x i8], [3072 x i8]* @buf, i64 0, i64 2048), i64 32, x86_amx %6)
|
||||
tail call void @foo()
|
||||
ret void
|
||||
}
|
||||
|
||||
define dso_local void @test2(i16 signext %0, i16 signext %1) nounwind {
|
||||
; CHECK-LABEL: test2:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: pushq %rbp
|
||||
; CHECK-NEXT: pushq %rbx
|
||||
; CHECK-NEXT: subq $72, %rsp
|
||||
; CHECK-NEXT: movl %esi, %ebx
|
||||
; CHECK-NEXT: movl %edi, %ebp
|
||||
; CHECK-NEXT: vpxord %zmm0, %zmm0, %zmm0
|
||||
; CHECK-NEXT: vmovdqu64 %zmm0, {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movb $1, {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movb $8, {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movw %bx, {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movb %bpl, {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movw %bx, {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movb %bpl, {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movw $8, {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movb $8, {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movw %bx, {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movb %bpl, {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movw $8, {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: vzeroupper
|
||||
; CHECK-NEXT: callq foo
|
||||
; CHECK-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: xorl %eax, %eax
|
||||
; CHECK-NEXT: testb %al, %al
|
||||
; CHECK-NEXT: jne .LBB1_3
|
||||
; CHECK-NEXT: # %bb.1: # %if.true
|
||||
; CHECK-NEXT: movw $8, %ax
|
||||
; CHECK-NEXT: tilezero %tmm0
|
||||
; CHECK-NEXT: movl $32, %ecx
|
||||
; CHECK-NEXT: movl $buf+1024, %edx
|
||||
; CHECK-NEXT: tileloadd (%rdx,%rcx), %tmm1
|
||||
; CHECK-NEXT: movl $buf+2048, %edx
|
||||
; CHECK-NEXT: tileloadd (%rdx,%rcx), %tmm2
|
||||
; CHECK-NEXT: tdpbssd %tmm2, %tmm1, %tmm0
|
||||
; CHECK-NEXT: tilestored %tmm0, (%rdx,%rcx)
|
||||
; CHECK-NEXT: jmp .LBB1_2
|
||||
; CHECK-NEXT: .LBB1_3: # %if.false
|
||||
; CHECK-NEXT: movl $buf, %eax
|
||||
; CHECK-NEXT: movl $32, %ecx
|
||||
; CHECK-NEXT: movw $8, %dx
|
||||
; CHECK-NEXT: tileloadd (%rax,%rcx), %tmm3
|
||||
; CHECK-NEXT: movl $buf+1024, %eax
|
||||
; CHECK-NEXT: tileloadd (%rax,%rcx), %tmm4
|
||||
; CHECK-NEXT: movl $buf+2048, %eax
|
||||
; CHECK-NEXT: tileloadd (%rax,%rcx), %tmm2
|
||||
; CHECK-NEXT: tdpbssd %tmm2, %tmm4, %tmm3
|
||||
; CHECK-NEXT: tilestored %tmm3, (%rax,%rcx)
|
||||
; CHECK-NEXT: .LBB1_2: # %if.true
|
||||
; CHECK-NEXT: addq $72, %rsp
|
||||
; CHECK-NEXT: popq %rbx
|
||||
; CHECK-NEXT: popq %rbp
|
||||
; CHECK-NEXT: tilerelease
|
||||
; CHECK-NEXT: retq
|
||||
call void @foo()
|
||||
br i1 undef, label %if.true, label %if.false
|
||||
|
||||
if.true:
|
||||
%t1 = tail call x86_amx @llvm.x86.tilezero.internal(i16 %0, i16 8)
|
||||
%t2 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 8, i16 %1, i8* getelementptr inbounds ([3072 x i8], [3072 x i8]* @buf, i64 0, i64 1024), i64 32)
|
||||
%t3 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 %0, i16 %1, i8* getelementptr inbounds ([3072 x i8], [3072 x i8]* @buf, i64 0, i64 2048), i64 32)
|
||||
%t4 = tail call x86_amx @llvm.x86.tdpbssd.internal(i16 %0, i16 %1, i16 8, x86_amx %t1, x86_amx %t2, x86_amx %t3)
|
||||
tail call void @llvm.x86.tilestored64.internal(i16 %0, i16 %1, i8* getelementptr inbounds ([3072 x i8], [3072 x i8]* @buf, i64 0, i64 2048), i64 32, x86_amx %t4)
|
||||
br label %exit
|
||||
|
||||
if.false:
|
||||
%t5 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 %0, i16 8, i8* getelementptr inbounds ([3072 x i8], [3072 x i8]* @buf, i64 0, i64 0), i64 32)
|
||||
%t6 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 8, i16 %1, i8* getelementptr inbounds ([3072 x i8], [3072 x i8]* @buf, i64 0, i64 1024), i64 32)
|
||||
%t7 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 %0, i16 %1, i8* getelementptr inbounds ([3072 x i8], [3072 x i8]* @buf, i64 0, i64 2048), i64 32)
|
||||
%t8 = tail call x86_amx @llvm.x86.tdpbssd.internal(i16 %0, i16 %1, i16 8, x86_amx %t5, x86_amx %t6, x86_amx %t7)
|
||||
tail call void @llvm.x86.tilestored64.internal(i16 %0, i16 %1, i8* getelementptr inbounds ([3072 x i8], [3072 x i8]* @buf, i64 0, i64 2048), i64 32, x86_amx %t8)
|
||||
br label %exit
|
||||
|
||||
exit:
|
||||
ret void
|
||||
}
|
||||
|
||||
declare dso_local void @foo() nounwind
|
||||
declare x86_amx @llvm.x86.tilezero.internal(i16, i16)
|
||||
declare x86_amx @llvm.x86.tileloadd64.internal(i16, i16, i8*, i64)
|
||||
declare x86_amx @llvm.x86.tdpbssd.internal(i16, i16, i16, x86_amx, x86_amx, x86_amx)
|
||||
declare void @llvm.x86.tilestored64.internal(i16, i16, i8*, i64, x86_amx)
|
||||
|
|
@ -36,11 +36,10 @@ define dso_local void @test_api(i16 signext %0, i16 signext %1) nounwind {
|
|||
; CHECK-NEXT: tileloadd (%r15,%r14), %tmm5
|
||||
; CHECK-NEXT: xorl %eax, %eax
|
||||
; CHECK-NEXT: testb %al, %al
|
||||
; CHECK-NEXT: sttilecfg {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Folded Spill
|
||||
; CHECK-NEXT: movl $buf, %eax
|
||||
; CHECK-NEXT: movw $8, %cx
|
||||
; CHECK-NEXT: jne .LBB0_2
|
||||
; CHECK-NEXT: # %bb.1: # %if.true
|
||||
; CHECK-NEXT: movl $buf, %eax
|
||||
; CHECK-NEXT: movw $8, %cx
|
||||
; CHECK-NEXT: tileloadd (%rax,%r14), %tmm0
|
||||
; CHECK-NEXT: movl $buf+1024, %eax
|
||||
; CHECK-NEXT: tileloadd (%rax,%r14), %tmm1
|
||||
|
|
@ -52,11 +51,13 @@ define dso_local void @test_api(i16 signext %0, i16 signext %1) nounwind {
|
|||
; CHECK-NEXT: xorl %eax, %eax
|
||||
; CHECK-NEXT: vzeroupper
|
||||
; CHECK-NEXT: callq foo
|
||||
; CHECK-NEXT: ldtilecfg {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Folded Reload
|
||||
; CHECK-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movabsq $64, %rax
|
||||
; CHECK-NEXT: tileloadd 1024(%rsp,%rax), %tmm6 # 1024-byte Folded Reload
|
||||
; CHECK-NEXT: jmp .LBB0_3
|
||||
; CHECK-NEXT: .LBB0_2: # %if.false
|
||||
; CHECK-NEXT: movl $buf, %eax
|
||||
; CHECK-NEXT: movw $8, %cx
|
||||
; CHECK-NEXT: tileloadd (%rax,%r14), %tmm2
|
||||
; CHECK-NEXT: movl $buf+1024, %eax
|
||||
; CHECK-NEXT: tileloadd (%rax,%r14), %tmm3
|
||||
|
|
@ -68,7 +69,7 @@ define dso_local void @test_api(i16 signext %0, i16 signext %1) nounwind {
|
|||
; CHECK-NEXT: xorl %eax, %eax
|
||||
; CHECK-NEXT: vzeroupper
|
||||
; CHECK-NEXT: callq foo
|
||||
; CHECK-NEXT: ldtilecfg {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Folded Reload
|
||||
; CHECK-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: movabsq $64, %rax
|
||||
; CHECK-NEXT: tileloadd 1024(%rsp,%rax), %tmm6 # 1024-byte Folded Reload
|
||||
; CHECK-NEXT: tilestored %tmm6, (%r15,%r14)
|
||||
|
|
@ -139,7 +140,6 @@ define dso_local void @test3(i8 *%buf) nounwind {
|
|||
; CHECK-NEXT: movq %rdi, %rbx
|
||||
; CHECK-NEXT: movl $32, %r14d
|
||||
; CHECK-NEXT: xorl %ebp, %ebp
|
||||
; CHECK-NEXT: sttilecfg {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Folded Spill
|
||||
; CHECK-NEXT: .p2align 4, 0x90
|
||||
; CHECK-NEXT: .LBB1_2: # %loop.header
|
||||
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
|
||||
|
|
@ -149,7 +149,7 @@ define dso_local void @test3(i8 *%buf) nounwind {
|
|||
; CHECK-NEXT: xorl %eax, %eax
|
||||
; CHECK-NEXT: vzeroupper
|
||||
; CHECK-NEXT: callq foo
|
||||
; CHECK-NEXT: ldtilecfg {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Folded Reload
|
||||
; CHECK-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: tilezero %tmm0
|
||||
; CHECK-NEXT: tileloadd (%rbx,%r14), %tmm1
|
||||
; CHECK-NEXT: tileloadd (%rbx,%r14), %tmm2
|
||||
|
|
|
|||
Loading…
Reference in New Issue