Silence warning.

llvm-svn: 111518
2010-08-19 15:35:27 +00:00 · 2010-08-19 15:35:27 +00:00 · a5d60c62b1
parent 448886d5df
commit a5d60c62b1
1 changed files with 1 additions and 1 deletions
--- a/llvm/lib/Target/ARM/ARMFastISel.cpp
+++ b/llvm/lib/Target/ARM/ARMFastISel.cpp
@ -137,7 +137,7 @@ ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
  
  // Do we optionally set a predicate?  Preds is size > 0 iff the predicate
  // defines CPSR. All other OptionalDefines in ARM are the CCR register.
-  bool CPSR;
+  bool CPSR = false;
  if (DefinesOptionalPredicate(MI, &CPSR)) {
    if (CPSR)
      AddDefaultT1CC(MIB);