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[AVR] Add tests for a large number of pseudo instructions 

This adds MIR tests for 24 pseudo instructions.

llvm-svn: 289191
This commit is contained in:
Dylan McKay 2016-12-09 07:49:04 +00:00
parent a55b483bb5
commit a5d49dfbb3
28 changed files with 572 additions and 4 deletions
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12
llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
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@ -703,6 +703,16 @@ bool AVRExpandPseudo::expand<AVR::LDDWRdPtrQ>(Block &MBB, BlockIt MBBI) {
return true;
}
template <>
bool AVRExpandPseudo::expand<AVR::LPMWRdZ>(Block &MBB, BlockIt MBBI) {
llvm_unreachable("wide LPM is unimplemented");
}
template <>
bool AVRExpandPseudo::expand<AVR::LPMWRdZPi>(Block &MBB, BlockIt MBBI) {
llvm_unreachable("wide LPMPi is unimplemented");
}
template<typename Func>
bool AVRExpandPseudo::expandAtomic(Block &MBB, BlockIt MBBI, Func f) {
// Remove the pseudo instruction.
@ -1415,6 +1425,8 @@ bool AVRExpandPseudo::expandMI(Block &MBB, BlockIt MBBI) {
EXPAND(AVR::LDWRdPtrPd);
case AVR::LDDWRdYQ: //:FIXME: remove this once PR13375 gets fixed
EXPAND(AVR::LDDWRdPtrQ);
EXPAND(AVR::LPMWRdZ);
EXPAND(AVR::LPMWRdZPi);
EXPAND(AVR::AtomicLoad8);
EXPAND(AVR::AtomicLoad16);
EXPAND(AVR::AtomicStore8);

3
llvm/test/CodeGen/AVR/progmem-extended.ll
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@ -1,4 +1,7 @@
; RUN: llc < %s -march=avr -mattr=movw,lpmx | FileCheck %s
; XFAIL: *
# Wide LPM is currently unimplemented in the pseudo expansion pass.
; Tests the extended LPM instructions (LPMW, LPM Rd, Z+).

22
llvm/test/CodeGen/AVR/pseudo/ASRWRd.mir Normal file
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@ -0,0 +1,22 @@
# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
--- |
target triple = "avr--"
define void @test() {
entry:
ret void
}
...
---
name: test
body: |
bb.0.entry:
; CHECK-LABEL: test
; CHECK: %r15 = ASRRd %r15, implicit-def %sreg
; CHECK-NEXT: %r14 = RORRd %r14, implicit-def %sreg, implicit killed %sreg
%r15r14 = ASRWRd %r15r14, implicit-def %sreg
...

6
llvm/test/CodeGen/AVR/pseudo/CPCWRdRr.mir
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@ -1,5 +1,4 @@
# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
# XFAIL: *
# This test checks the expansion of the 16-bit CPCW pseudo instruction.
@ -18,5 +17,8 @@ body: |
; CHECK-LABEL: test_cpcwrdrr
%r15r14 = CPCWRdRr %r15r14, %r21r20, implicit-def %sreg, implicit %sreg
; CHECK: CPCRdRr %r20, %r22, implicit-def %sreg, implicit killed %sreg
; CHECK-NEXT: CPCRdRr %r21, %r23, implicit-def %sreg, implicit killed %sreg
CPCWRdRr %r21r20, %r23r22, implicit-def %sreg, implicit %sreg
...

6
llvm/test/CodeGen/AVR/pseudo/CPWRdRr.mir
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@ -1,5 +1,4 @@
# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
# XFAIL: *
# This test checks the expansion of the 16-bit CPW pseudo instruction.
@ -18,5 +17,8 @@ body: |
; CHECK-LABEL: test_cpwrdrr
%r15r14 = CPWRdRr %r15r14, %r21r20, implicit-def %sreg
; CHECK: CPRdRr %r14, %r20, implicit-def %sreg
; CHECK-NEXT: CPCRdRr %r15, %r21, implicit-def %sreg, implicit killed %sreg
CPWRdRr %r15r14, %r21r20, implicit-def %sreg
...

25
llvm/test/CodeGen/AVR/pseudo/FRMIDX.mir Normal file
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@ -0,0 +1,25 @@
# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
# TODO: Write this test.
# This instruction isn't expanded by the pseudo expansion passs, but
# rather AVRRegisterInfo::eliminateFrameIndex.
--- |
target triple = "avr--"
define void @test() {
entry:
ret void
}
...
---
name: test
registers:
- { id: 0, class: _ }
body: |
bb.0.entry:
; CHECK-LABEL: test
%r29r28 = FRMIDX %r31r30, 0, implicit-def %sreg
...

22
llvm/test/CodeGen/AVR/pseudo/INWRdA.mir Normal file
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@ -0,0 +1,22 @@
# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
--- |
target triple = "avr--"
define void @test() {
entry:
ret void
}
...
---
name: test
body: |
bb.0.entry:
; CHECK-LABEL: test
; CHECK: %r14 = INRdA 31
; CHECK-NEXT: %r15 = INRdA 32
%r15r14 = INWRdA 31
...

24
llvm/test/CodeGen/AVR/pseudo/LDIWRdK.mir Normal file
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@ -0,0 +1,24 @@
# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
# This test checks the expansion of the 16-bit LDIWRdK pseudo instruction.
--- |
target triple = "avr--"
define void @test_ldiwrdrr() {
entry:
ret void
}
...
---
name: test_ldiwrdrr
body: |
bb.0.entry:
; CHECK-LABEL: test_ldiwrdrr
; CHECK: %r30 = LDIRdK 255
; CHECK-NEXT: %r31 = LDIRdK 9
%r31r30 = LDIWRdK 2559
...

24
llvm/test/CodeGen/AVR/pseudo/LDSWRdK.mir Normal file
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@ -0,0 +1,24 @@
# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
# This test checks the expansion of the 16-bit LDSWRdK pseudo instruction.
--- |
target triple = "avr--"
define void @test_ldswrdrr() {
entry:
ret void
}
...
---
name: test_ldswrdrr
body: |
bb.0.entry:
; CHECK-LABEL: test_ldswrdrr
; CHECK: %r30 = LDSRdK 2559
; CHECK-NEXT: %r31 = LDSRdK 2560
%r31r30 = LDSWRdK 2559
...

24
llvm/test/CodeGen/AVR/pseudo/LDWRdPtr.mir Normal file
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@ -0,0 +1,24 @@
# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
# This test checks the expansion of the 16-bit LDWRdPtr pseudo instruction.
--- |
target triple = "avr--"
define void @test_ldwrdptr() {
entry:
ret void
}
...
---
name: test_ldwrdptr
body: |
bb.0.entry:
; CHECK-LABEL: test_ldwrdptr
; CHECK: %r0 = LDRdPtr %r31r30
; CHECK-NEXT: early-clobber %r1 = LDDRdPtrQ %r31r30, 1
%r1r0 = LDWRdPtr %r31r30
...

24
llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir Normal file
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@ -0,0 +1,24 @@
# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
# This test checks the expansion of the 16-bit LDWRdPtrPd pseudo instruction.
--- |
target triple = "avr--"
define void @test_ldwrdptrpd() {
entry:
ret void
}
...
---
name: test_ldwrdptrpd
body: |
bb.0.entry:
; CHECK-LABEL: test_ldwrdptrpd
; CHECK: early-clobber %r1, early-clobber %r31r30 = LDRdPtrPd killed %r31r30
; CHECK-NEXT: early-clobber %r0, early-clobber %r31r30 = LDRdPtrPd killed %r31r30
%r1r0, %r31r30 = LDWRdPtrPd %r31r30
...

24
llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir Normal file
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@ -0,0 +1,24 @@
# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
# This test checks the expansion of the 16-bit LDWRdPtrPi pseudo instruction.
--- |
target triple = "avr--"
define void @test_ldwrdptrpi() {
entry:
ret void
}
...
---
name: test_ldwrdptrpi
body: |
bb.0.entry:
; CHECK-LABEL: test_ldwrdptrpi
; CHECK: early-clobber %r0, early-clobber %r31r30 = LDRdPtrPi killed %r31r30
; CHECK-NEXT: early-clobber %r1, early-clobber %r31r30 = LDRdPtrPi killed %r31r30
%r1r0, %r31r30 = LDWRdPtrPi %r31r30
...

22
llvm/test/CodeGen/AVR/pseudo/LPMWRdZ.mir Normal file
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@ -0,0 +1,22 @@
# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
# XFAIL: *
# This instruction is currently unimplemented.
--- |
target triple = "avr--"
define void @test() {
entry:
ret void
}
...
---
name: test
body: |
bb.0.entry:
; CHECK-LABEL: test
%r5r4 = LPMWRdZ %r31r30
...

22
llvm/test/CodeGen/AVR/pseudo/LPMWRdZPi.mir Normal file
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@ -0,0 +1,22 @@
# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
# XFAIL: *
# This instruction is currently unimplemented.
--- |
target triple = "avr--"
define void @test() {
entry:
ret void
}
...
---
name: test
body: |
bb.0.entry:
; CHECK-LABEL: test
%r5r4 = LPMWRdZPi %r31r30, implicit-def %r31r30
...

22
llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir Normal file
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@ -0,0 +1,22 @@
# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
--- |
target triple = "avr--"
define void @test() {
entry:
ret void
}
...
---
name: test
body: |
bb.0.entry:
; CHECK-LABEL: test
; CHECK: %r14 = LSLRd %r14, implicit-def %sreg
; CHECK-NEXT: %r15 = ROLRd %r15, implicit-def %sreg, implicit killed %sreg
%r15r14 = LSLWRd %r15r14, implicit-def %sreg
...

22
llvm/test/CodeGen/AVR/pseudo/LSRWRd.mir Normal file
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@ -0,0 +1,22 @@
# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
--- |
target triple = "avr--"
define void @test() {
entry:
ret void
}
...
---
name: test
body: |
bb.0.entry:
; CHECK-LABEL: test
; CHECK: %r15 = LSRRd %r15, implicit-def %sreg
; CHECK-NEXT: %r14 = RORRd %r14, implicit-def %sreg, implicit killed %sreg
%r15r14 = LSRWRd %r15r14, implicit-def %sreg
...

22
llvm/test/CodeGen/AVR/pseudo/OUTWARr.mir Normal file
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@ -0,0 +1,22 @@
# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
--- |
target triple = "avr--"
define void @test() {
entry:
ret void
}
...
---
name: test
body: |
bb.0.entry:
; CHECK-LABEL: test
; CHECK: OUTARr 32, %r15
; CHECK-NEXT: OUTARr 31, %r14
OUTWARr 31, %r15r14
...

22
llvm/test/CodeGen/AVR/pseudo/POPWRd.mir Normal file
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@ -0,0 +1,22 @@
# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
--- |
target triple = "avr--"
define void @test() {
entry:
ret void
}
...
---
name: test
body: |
bb.0.entry:
; CHECK-LABEL: test
; CHECK: %r29 = POPRd implicit-def %sp, implicit %sp
; CHECK-LABEL: %r28 = POPRd implicit-def %sp, implicit %sp
%r29r28 = POPWRd implicit-def %sp, implicit %sp
...

22
llvm/test/CodeGen/AVR/pseudo/PUSHWRr.mir Normal file
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@ -0,0 +1,22 @@
# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
--- |
target triple = "avr--"
define void @test() {
entry:
ret void
}
...
---
name: test
body: |
bb.0.entry:
; CHECK-LABEL: test
; CHECK: PUSHRr %r28, implicit-def %sp, implicit %sp
; CHECK-NEXT: PUSHRr %r29, implicit-def %sp, implicit %sp
PUSHWRr %r29r28, implicit-def %sp, implicit %sp
...

22
llvm/test/CodeGen/AVR/pseudo/ROLWRd.mir Normal file
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@ -0,0 +1,22 @@
# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
# XFAIL: *
# This instruction is unimplemented.
--- |
target triple = "avr--"
define void @test() {
entry:
ret void
}
...
---
name: test
body: |
bb.0.entry:
; CHECK-LABEL: test
%r15r14 = ROLWRd %r15r14, implicit-def %sreg, implicit %sreg
...

22
llvm/test/CodeGen/AVR/pseudo/RORWRd.mir Normal file
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@ -0,0 +1,22 @@
# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
# XFAIL: *
# This instruction is unimplemented.
--- |
target triple = "avr--"
define void @test() {
entry:
ret void
}
...
---
name: test
body: |
bb.0.entry:
; CHECK-LABEL: test
%r15r14 = RORWRd %r15r14, implicit-def %sreg, implicit %sreg
...

24
llvm/test/CodeGen/AVR/pseudo/SEXT.mir Normal file
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@ -0,0 +1,24 @@
# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
--- |
target triple = "avr--"
define void @test() {
entry:
ret void
}
...
---
name: test
body: |
bb.0.entry:
; CHECK-LABEL: test
; CHECK: %r14 = MOVRdRr %r31
; CHECK-NEXT: %r15 = MOVRdRr %r31
; CHECK-NEXT: %r15 = LSLRd killed %r15, implicit-def %sreg
; CHECK-NEXT: %r15 = SBCRdRr killed %r15, killed %r15, implicit-def %sreg, implicit killed %sreg
%r15r14 = SEXT %r31, implicit-def %sreg
...

22
llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir Normal file
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@ -0,0 +1,22 @@
# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
--- |
target triple = "avr--"
define void @test() {
entry:
ret void
}
...
---
name: test
body: |
bb.0.entry:
; CHECK-LABEL: test
; CHECK: STDPtrQRr %r29r28, 10, %r0
; CHECK-NEXT: STDPtrQRr %r29r28, 11, %r1
STDWPtrQRr %r29r28, 10, %r1r0
...

24
llvm/test/CodeGen/AVR/pseudo/STSWKRr.mir Normal file
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@ -0,0 +1,24 @@
# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
# This test checks the expansion of the 16-bit STSWRdK pseudo instruction.
--- |
target triple = "avr--"
define void @test_stswkrr() {
entry:
ret void
}
...
---
name: test_stswkrr
body: |
bb.0.entry:
; CHECK-LABEL: test_stswkrr
; CHECK: STSKRr 2560, %r31
; CHECK-NEXT: STSKRr 2559, %r30
STSWKRr 2559, %r31r30
...

22
llvm/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir Normal file
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@ -0,0 +1,22 @@
# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
--- |
target triple = "avr--"
define void @test() {
entry:
ret void
}
...
---
name: test
body: |
bb.0.entry:
; CHECK-LABEL: test
; CHECK: early-clobber %r31r30 = STPtrPdRr killed %r31r30, %r29, 52
; CHECK-NEXT: early-clobber %r31r30 = STPtrPdRr killed %r31r30, %r28, 52
%r31r30 = STWPtrPdRr %r31r30, %r29r28, 52
...

22
llvm/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir Normal file
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@ -0,0 +1,22 @@
# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
--- |
target triple = "avr--"
define void @test() {
entry:
ret void
}
...
---
name: test
body: |
bb.0.entry:
; CHECK-LABEL: test
; CHECK: early-clobber %r31r30 = STPtrPiRr killed %r31r30, %r28, 52
; CHECK-NEXT: early-clobber %r31r30 = STPtrPiRr killed %r31r30, %r29, 52
%r31r30 = STWPtrPiRr %r31r30, %r29r28, 52
...

24
llvm/test/CodeGen/AVR/pseudo/STWPtrRr.mir Normal file
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@ -0,0 +1,24 @@
# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
# This test checks the expansion of the 16-bit STSWRdK pseudo instruction.
--- |
target triple = "avr--"
define void @test_stwptrrr() {
entry:
ret void
}
...
---
name: test_stwptrrr
body: |
bb.0.entry:
; CHECK-LABEL: test_stwptrrr
; CHECK: STPtrRr %r31r30, %r16
; CHECK-NEXT: STDPtrQRr %r31r30, 1, %r17
STWPtrRr %r31r30, %r17r16
...

24
llvm/test/CodeGen/AVR/pseudo/ZEXT.mir Normal file
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@ -0,0 +1,24 @@
# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
--- |
target triple = "avr--"
define void @test() {
entry:
ret void
}
...
---
name: test
body: |
bb.0.entry:
; CHECK-LABEL: test
; CHECK: %r14 = MOVRdRr %r31
; CHECK-NEXT: %r15 = MOVRdRr %r31
; CHECK-NEXT: %r15 = LSLRd killed %r15, implicit-def %sreg
; CHECK-NEXT: %r15 = SBCRdRr killed %r15, killed %r15, implicit-def %sreg, implicit killed %sreg
%r15r14 = SEXT %r31, implicit-def %sreg
...